Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 41
USB3320
During transmit the transceiver will use NXT to control the rate of data flow into the transceiver. If the USB3320 pipeline
is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until
NXT is asserted. The USB Transmit ends when the Link asserts STP while NXT is asserted.
After the USB3320 completes transmitting, the DP and DM lines return to idle and a RXCMD is returned to the Link so
the inter-packet timers may be updated by linestate.
While operating in Full Speed or Low Speed, an End-of-Packet (EOP) is defined as SE0 for approximately two bit times,
followed by J for one bit time. The transceiver drives a J state for one bit time following the SE0 to complete the EOP.
The Link must wait for one bit time following line state indication of the SE0 to J transition to allow the transceiver to
complete the one bit time J state. All bit times are relative to the speed of transmission.
In the case of Full Speed or Low Speed, after STP is asserted each FS/LS bit transition will generate a RXCMD since
the bit times are relatively slow.
6.2.5 USB RECEIVER
The USB3320 ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the receiver detects
the start of packet and synchronizes to the incoming data packet. In the ULPI protocol, a received packet has the priority
and will immediately follow register reads and RXCMD transfers. Figure 6-8 shows a basic USB packet received by the
USB3320 over the ULPI interface.
FIGURE 6-7: ULPI TRANSMIT IN SYNCHRONOUS MODE
Note: The Link cannot assert STP with NXT de-asserted since the USB3320 is expecting to fetch another byte
from the Link.
DATA[7:0]
DP/DM
DIR
CLK
STP
NXT
TXD CMD
(USB tx)
Idle
D0 D2 D3 IDLE
SE0
!SQUELCH
SE0
Turn
Around
Turn
Around
RXD
CMD
D1