Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
USB3320
DS00001792E-page 40 2014-2016 Microchip Technology Inc.
6.2.4.1 High Speed Long EOP
When operating as a Hi-Speed host, the USB3320 will automatically generate a 40 bit long End of Packet (EOP) after
a SOF PID (A5h). The USB3320 determines when to send the 40-bit long EOP by decoding the ULPI TXD CMD bits
[3:0] for the SOF. The 40-bit long EOP is only transmitted when the DpPulldown and DmPulldown bits in the OTG Con-
trol register are asserted. The Hi-Speed 40-bit long EOP is used to detect a disconnect in high speed mode.
In device mode, the USB3320 will not send a long EOP after a SOF PID.
6.2.4.2 Low Speed Keep-Alive
Low speed keep alive is supported by the USB3320. When in Low speed (XcvrSelect = 10b in the Function Control
register), the USB3320 will send out two Low speed bit times of SE0 when a SOF PID is received.
6.2.4.3 UTMI+ Level 3
Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect = 11b in the Function Control register in host
mode (DpPulldown and DmPulldown both asserted), the USB3320 will pre-pend a full speed pre-amble before the low
speed packet. Full speed rise and fall times are used in this mode. The pre-amble consists of the following: Full speed
sync, the encoded pre-PID (C3h) and then full speed idle (DP=1 and DM = 0). A low speed packet follows with a sync,
data and a LS EOP.
The USB3320 will only support UTMI+ Level 3 as a host. The USB3320 does not support UTMI+ Level 3 as a peripheral.
A UTMI+ Level 3 peripheral is an upstream hub port. The USB3320 will not decode a pre-amble packet intended for a
LS device when the USB3320 is configured as the upstream port of a FS hub, XcvrSelect = 11b, DpPulldown = 0b,
DmPulldown =0b.
6.2.4.4 Host Resume K
Resume K generation is supported by the USB3320. When the USB3320 exits the suspended (Low Power Mode), the
USB3320, when operating as a host, will transmit a K on DP/DM. The transmitters will end the K with SE0 for two Low
Speed bit times. If the USB3320 was operating in high speed mode before the suspend, the host must change to high
speed mode before the SE0 ends. SE0 is two low speed bit times which is about 1.2 us. For more details please see
sections 7.1.77 and 7.9 of the USB Specification.
In device mode, the resume K will not append an SE0, but release the bus to the correct idle state, depending upon the
operational mode as shown in Tab le 5- 1.
The ULPI specification includes a detailed discussion of the resume sequence and the order of operations required. To
support Host start-up of less than 1mS the USB3320 implements the ULPI AutoResume bit in the Interface Control reg-
ister. The default AutoResume state is 0 and this bit should be enabled for Host applications.
6.2.4.5 No SYNC and EOP Generation (OpMode = 11)
UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This is an option to the
ULPI specification and not implemented in the USB3320.
6.2.4.6 Typical USB Transmit with ULPI
Figure 6-7 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a TXD CMD where
DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMD with the PID is followed by transmit data.