Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service

USB3320
DS00001792E-page 38 2014-2016 Microchip Technology Inc.
At T0, the Link will place the TXD CMD on the data bus. At T2, the transceiver will bring NXT high, signaling the Link it
is ready to accept the data transfer. At T3, the transceiver reads the TXD CMD, determines it is a register read, and
asserts DIR to gain control of the bus. The transceiver will also de-assert NXT. At T4, the bus ownership has transferred
back to the transceiver and the transceiver drives the requested register onto the data bus. At T5, the Link will read the
data bus and the transceiver will drop DIR low returning control of the bus back to the Link. After the turn around cycle,
the Link must drive a ULPI Idle command at T6.
A ULPI extended register read operation is shown in Figure 6-6.To read an extended register, the Link writes the TX
CMD with the address set to 2Fh. At T2, the transceiver will assert NXT, signaling the Link it is ready to accept the
extended address. At T3, the Link places the extended register address on the bus. At T4, the transceiver reads the
extended address, and asserts DIR to gain control of the bus. The transceiver will also de-assert NXT. At T5, the bus
ownership has transferred back to the transceiver and the transceiver drives the requested register onto the data bus.
At T6, the Link will read the data bus and the transceiver will de-assert DIR returning control of the bus back to the Link.
After the turn around cycle, the Link must drive a ULPI Idle command at T6.
6.2.3 ULPI RXCMD
The ULPI Link needs information which was provided by the following pins in a UTMI implementation: linestate[1:0],
rxactive, rxvalid and rxerror. When implementing the OTG functions, the VBUS and ID pin states must also be trans-
ferred to the Link.
ULPI defines a Receive Command Byte (RXCMD) that contains this information. The Encoding of the RXCMD byte is
given in the Tab le 6- 3.
Transfer of the RXCMD byte occurs in Synchronous Mode when the transceiver has control of the bus. The ULPI Pro-
tocol Block shown in Figure 6-1 determines when to send an RXCMD.
A RXCMD can occur:
• When a linestate change occurs.
• When VBUS or ID comparators change state.
• During a USB receive when NXT is low.
• After the USB3320 deasserts DIR and STP is low during start-up
• After the USB3320 exits Low Power Mode, Serial Modes, or Carkit Mode after detecting that the Link has de-
asserted STP, and DIR is low.
When a USB Receive is occurring, RXCMD’s are sent whenever NXT = 0 and DIR = 1. During a USB Transmit, the
RXCMD’s are returned to the Link after STP is asserted.
FIGURE 6-6: ULPI EXTENDED REGISTER READ IN SYNCHRONOUS MODE
DIR
CLK
DATA[7:0]
STP
NXT
TXD CMD
extended reg read
Idle
T0
Reg DataTurn around Turn around
T1 T2 T3 T4 T5 T6
Idle
Extended
address
T7