Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 35
USB3320
6.1.2 ULPI INTERFACE TIMING IN SYNCHRONOUS MODE
The control and data timing relationships are given in Figure 6-2 and Ta bl e 4 -3 . All timing is relative to the rising clock
edge of the 60MHz ULPI Clock.
6.2 ULPI Register Access
A command from the Link begins a ULPI transfer from the Link to the USB3320. Before reading a ULPI register, the Link
must wait until DIR is low, and then send a Transmit Command Byte (TXD CMD) byte. The TXD CMD byte informs the
USB3320 of the type of data being sent. The TXD CMD is followed by a data transfer to or from the USB3320. Ta bl e 6-
2 gives the TXD command byte (TXD CMD) encoding for the USB3320. The upper two bits of the TX CMD instruct the
transceiver as to what type of packet the Link is transmitting. The ULPI registers retain their contents when the trans-
ceiver is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode.
FIGURE 6-2: ULPI SINGLE DATA RATE TIMING DIAGRAM IN SYNCHRONOUS MODE
TABLE 6-2: ULPI TXD CMD BYTE ENCODING
Command Name CMD Bits[7:6] CMD Bits[5:0] Command Description
Idle 00b 000000b ULPI Idle
Transmit 01b 000000b USB Transmit Packet with No Packet Identifier (NOPID)
00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0]
is equal to the 4-bit PID. P
3
P
2
P
1
P
0
where P
3
is the
MSB.
Register Write 10b XXXXXXb Immediate Register Write Command where: DATA[5:0]
= 6-bit register address
101111b Extended Register Write Command where the 8-bit
register address is available on the next cycle.
Register Read 11b XXXXXXb Immediate Register Read Command where: DATA[5:0]
= 6-bit register address
101111b Extended Register Read Command where the 8-bit
register address is available on the next cycle.
60MHz ULPI -
CLK
Control In -
STP
Data In -
DATA[7:0]
Control Out -
DIR, NXT
Data Out -
DATA[7:0]
T
SC
T
SD
T
HC
T
HD
T
DC
T
DC
T
DD