Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service

2014-2016 Microchip Technology Inc. DS00001792E-page 33
USB3320
6.0 ULPI OPERATION
6.1 Overview
The USB3320 uses the industry standard ULPI digital interface to facilitate communication between the USB Trans-
ceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the number of pins required to con-
nect a discrete USB Transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface
requires 54 signals while a ULPI interface requires only 12 signals.
The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1”. The
following sections describe the operating modes of the USB3320 digital interface.
Figure 6-1 illustrates the block diagram of the ULPI digital functions. It should be noted that this USB3320 does not use
a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.
The advantage of a “wrapper less” architecture is that the USB3320 has a lower USB latency than a design which must
first register signals into the PHY’s wrapper before the transfer to the PHY core. A low latency PHY allows a Link to use
a wrapper around a UTMI Link and still make the required USB turn-around timing given in the USB 2.0 specification.
FIGURE 6-1: ULPI DIGITAL BLOCK DIAGRAM
NOTE:
The ULPI interface
is a wrapperless
design.
POR
ULPI Register Array
Interrupt Control
6pinSerial Mode
XcvrSelect[1:0]
TermSelect
OpMode[1:0]
Reset
SuspendM
3pinSerial Mode
ClockSuspendM
AutoResume
DischrgVbus
ChrgVbus
IdGndDrv
SpkLeftEn
SpkRightEn/MicEn
DpPulldown
DmPulldown
SwapDP/DM
CarkitMode
RegOutput[1:0]
ChargerPullupEnDP
ChargerPullupEnDM
TxdEn
RxdEn
Indicator Complement
Indicator Pass Thru
UseExternal Vbus Indicator
IdPullUp
Linestates[1:0]
HostDisconnect
Interface Protect Disable
VbusValid
SessionValid
SessionEnd
IdGnd
IdFloat
RidCon...Start
RidValue[2:0]
RidCon...Done
Data[7:0]
High Speed TX
Full Speed TX
Low Speed TX
High Speed Data
Recovery
Full / Low Speed
Data Recovery
ULPI Protocol
Block
HS Tx Data
FS/LS Tx Data
HS RX Data
FS/LS Data
DIR
NXT
STP
Tx Data
Rx Data
USB Transmit and Receive Logic
ULPI Register Access
RESETB
ULPI Interupt
Rid State
Machine
To RX
Analog
To TX
Analog
Transceiver Control
To
OTG
Analog
To USB
Audio
Analog