Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
USB3320
DS00001792E-page 32 2014-2016 Microchip Technology Inc.
During normal USB operation the switches are off. When USB Audio is desired the switches can be turned “on” by
enabling the SpkLeftEn, SpkRightEn, or MicEn bits in the Carkit Control register as described in Section 6.5.2. These
bits are disabled by default. The USB Audio Switches can also be enabled by asserting the RESETB pin or removing
the voltage at VDD18 as shown in Table 5-9. While using the USB switches, VDD18 is not required, but 3.3V must be
present at VDD33. The integrated 3.3V LDO regulator may be used to generate VDD33 from power applied at the VBAT
pin.
In addition to USB Audio support the switches can also be used to multiplexed a second FS USB transceiver to the USB
connector. The signal quality will be degraded slightly due to the “on” resistance of the switches. The USB3320 single-
ended receivers described in Section 5.2.1 are disabled when either USB Audio switch is enabled.
The USB3320 does not provide the DC bias for the audio signals. The SPK_R and SPK_L pins should be biased to
1.65V when audio signals are routed through the USB3320. This DC bias is necessary to prevent the audio signal from
swinging below ground and being clipped by ESD Diodes.
When the system is not using the USB Audio switches, the SPK_R and SPK_L pins should not be connected.
5.10 Reference Frequency Selection
The USB3320 is configured for the desired reference frequency by the REFSEL[2], REFSEL[1] and REFSEL[0] pins.
If a pin is connected to VDDIO, the value of “1” is assigned. Connect the pin to ground to assign a “0.” When using the
ULPI Input Clock Mode (60MHz REFCLK Mode), the reference frequency is always fixed at 60 MHz. Eight reference
clock frequencies are available as described in Ta ble 5- 10 .
TABLE 5-9: USB AUDIO SWITCH ENABLE
RESETB VDD18 DP Switch Enable DM Switch Enable
X011
0111
11SpkLeftEn SpkRightEn or MicEn
Note: SpkLeftEn, SpkRightEn, and MicEn are enabled in the Carkit Control register.
TABLE 5-10: CONFIGURATION TO SELECT REFERENCE CLOCK FREQUENCY
Configuration Pins Description
REFSEL[2] REFSEL[1] REFSEL[0] Reference Frequency
0 0 0 52 MHz
0 0 1 38.4 MHz
0 1 0 12 MHz
0 1 1 27 MHz
1 0 0 13 MHz
1 0 1 19.2 MHz
1 1 0 26 MHz
1 1 1 24 MHz