Datasheet

 2014-2016 Microchip Technology Inc. DS00001792E-page 25
USB3320
Note 5-2 VDDIO must be powered to tri-state the ULPI interface in this configuration.
5.5.4 START-UP
The power on default state of the USB3320 is ULPI Synchronous mode. The USB3320 requires the following conditions
to begin operation: the power supplies must be stable, the REFCLK must be present and the RESETB pin must be high.
After these conditions are met, the USB3320 will begin ULPI operation that is described in Section 6.0, "ULPI Opera-
tion".
Figure 5-9 below shows a timing diagram to illustrate the start-up of the USB3320. At T0, the supplies are stable and
the USB3320 is held in reset mode. At T1, the Link drives RESETB high after the REFCLK has started. The RESETB
pin may be brought high asynchronously to REFCLK. At this point the USB3320 will drive idle on the data bus and assert
DIR until the internal PLL has locked. After the PLL has locked, the USB3320 will check that the Link has de-asserted
STP and at T2 it will de-assert DIR and begin ULPI operation.
The ULPI bus will be available as shown in Figure 5-9 in the time defined as T
START
given in Table 4-2. If the REFCLK
signal starts after the RESETB pin is brought high, then time T0 will begin when REFCLK starts. T
START
also assumes
that the Link has de-asserted STP. If the Link has held STP high the USB3320 will hold DIR high until STP is de-
asserted. When the LINK de-asserts STP, it must drive a ULPI IDLE one cycle after DIR de-asserts.
1 1 0 RESET Mode
1 1 1 Full USB operation as described in Section 6.0, "ULPI
Operation".
Note: Anytime VBAT is powered per Table 3-2, the VDD33 pin will be powered up.
FIGURE 5-9: ULPI START-UP TIMING
TABLE 5-3: OPERATING MODE VS. POWER SUPPLY CONFIGURATION (CONTINUED)
VDD33 VDD18 RESETB Operating Modes Available
DIR
RESETB
STP
T
START
REFCLK
T1 T2
T0
SUPPLIES
STABLE
PHY Drives Idle
DATA[7:0]
REFCLK valid
PHY Tri-States
PHY Tri-States
PHY Drives High
LINK Drives Low
RXCMDIDLE IDLE