Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
USB3320
DS00001792E-page 24 2014-2016 Microchip Technology Inc.
The VBAT input must never be exposed to a voltage that exceeds V
VBAT
. (See Ta ble 3- 2)
5.5.2 POWER ON RESET (POR)
The USB3320 provides a POR circuit that generates an internal reset pulse after the VDD18 supply is stable. After the
internal POR goes high and the RESETB pin is high, the USB3320 will release from reset and begin normal ULPI oper-
ation as described in Section 5.5.4.
The ULPI registers will power up in their default state summarized in Table 7-1 when the 1.8V supply is brought up.
Cycling the 1.8 volt power supply will reset the ULPI registers to their default states. The RESETB pin can also be used
to reset the ULPI registers to their default state (and reset all internal state machines) by bringing the pin low for a min-
imum of 1 microsecond and then high.
The Link is not required to assert the RESETB pin. A pull-down resistor is not present on the RESETB pin and therefore
the Link must drive the RESETB pin to the desired state at all times (including system start-up) or connect the RESETB
pin to VDDIO.
5.5.3 RECOMMENDED POWER SUPPLY SEQUENCE
For USB operation the USB3320 requires the VBAT, VDD33, VDDIO and VDD18 supples. VBAT, VDD33, and VDD18
can be applied in any order. The VDD18 supply must be turned on and stable before the VDDIO supply is applied. This
does not apply in cases where the VDD18 and VDDIO supply pins are tied together.
When the VBAT supply is applied, the integrated regulator will automatically start-up and regulate VBAT to VDD33. If
the VDD33 supply is powered and the VDD18 supply is not powered, the 3.3V circuits are powered off and the VDD33
current will be limited as shown in Ta ble 4- 1.
The ULPI interface will start operating after the VDD18 and VDDIO supplies are applied and the RESETB pin is brought
high. The RESETB pin must be held low until the VDD18 and VDDIO supplies are stable. If the Link is not ready to
interface the USB3320, the Link may choose to hold the RESETB pin low until it is ready to control the ULPI interface.
FIGURE 5-8: POWERING THE USB3320 FROM VBUS
TABLE 5-3: OPERATING MODE VS. POWER SUPPLY CONFIGURATION
VDD33 VDD18 RESETB Operating Modes Available
0 0 0 Powered Off
0 1 0 RESET Mode.
0 1 1 In this configuration the ULPI interface is available and can
be programed into all operating modes described in Section
6.0, "ULPI Operation". All USB signals will read 0.
1 0 X In this mode the ULPI interface is not active and the circuits
powered from the VDD33 supply are turned off and the
current will be limited to the RESET Mode current. (Note 5-2)
VBUS
VDD33
VBAT
GND
LDO
~
~
~
~
PHY
To OTG
C
OUT
OVP
VBUS
To USB Con.
R
VBUS