Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
USB3320
DS00001792E-page 22 2014-2016 Microchip Technology Inc.
5.4.3 REFCLK JITTER
The USB3320 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of
less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Input Clock
Mode or ULPI Output Clock Mode, the USB3320 Hi-Speed eye diagram may be degraded.
The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Ta bl e 4 -2 .
5.4.4 REFCLK ENABLE/DISABLE
The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start running after the
time specified in Tabl e 4 -2. If the REFCLK enable is delayed relative to the RESETB pin, the ULPI interface will start
operation delayed by the same amount. The REFCLK can be run at anytime the RESETB pin is low without causing
the USB3320 to start-up or draw current.
When the USB3320 is placed in Low Power Mode or Carkit Mode, the REFCLK can be stopped after the final ULPI
register write is complete. The STP pin is asserted to bring the USB3320 out of Low Power Mode. The REFCLK should
be started at the same time STP is asserted to minimize the USB3320 start-up time.
If the REFCLK is stopped while CLKOUT is running, the PLL will come out of lock and the frequency of the CLKOUT
signal will decrease to the minimum allowed by the PLL design. If the REFCLK is stopped during a USB session, the
session may drop.
5.5 Internal Regulators and POR
The USB3320 includes integrated power management functions, including a Low-Dropout regulator that can be used
to generate the 3.3V USB supply, and a POR generator described in Section 5.5.2.
5.5.1 INTEGRATED LOW DROPOUT REGULATOR
The USB3320 has an integrated linear regulator. Power sourced at the VBAT pin is regulated to 3.3V and the regulator
output is on the VDD33 pin. To ensure stability, the regulator requires an external bypass capacitor (C
OUT)
as specified
in Table 4-9 placed as close to the pin as possible.
The USB3320 regulator is designed to generate a 3.3 volt supply for the USB3320 only. Using the regulator to provide
current for other circuits is not recommended and Microchip does not support USB performance or regulator stability.
During USB UART mode the regulator output voltage can be changed to allow the USB3320 to work with UARTs oper-
ating at different operating voltages. The regulator output is configured to the voltages shown in Ta bl e 4- 9 with the UART
RegOutput[1:0] bits in the USB IO & Power Management register.
The USB3320 regulator can be powered in the three methods as shown below.
For USB Peripheral, Host, and OTG operations the regulator can be connected as shown in Figure 5-6 or Figure 5-7
below. For OTG operation, the VDD33 supply on the USB3320 must be powered to detect devices attaching to the USB
connector and detect a SRP during an OTG session. When using a battery to supply the USB3320, the battery voltage
must be within the range of 3.1V to 5.5V.