Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 21
USB3320
In this mode, the REFCLK pin may be driven at the reference clock frequency. Alternatively, the internal oscillator may
be used with an external crystal or resonator as shown in Figure 5-4.
An example of ULPI Output Clock Mode is shown in Figure 8-1.
After the PLL has locked to the correct frequency, the USB3320 generates the 60MHz ULPI clock on the CLKOUT pin,
and de-asserts DIR to indicate that the PLL is locked. The USB3320 is ensured to start the clock within the time specified
in Tab le 4- 2, and it will be accurate to within ±500ppm. For Host applications the ULPI AutoResume bit should be
enabled. This is described in Section 6.2.4.4.
When using ULPI Output Clock Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI
interface signals; in other words, there is no need to align the phase of the REFCLK and the CLKOUT.
5.4.2 REFCLK AMPLITUDE
The reference clock is connected to the REFCLK pin as shown in the application diagrams, Figure 8-1, Figure 8-2 and
Figure 8-3. The REFCLK pin is designed to be driven with a square wave from 0V to V
DD18
, but can be driven with a
square wave from 0V to as high as 3.6V. The USB3320 uses only the positive edge of the REFCLK.
If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the
REFCLK pin. If using an analog clock, the DC bias should be set at the mid-point of the VDD18 supply using a bias
circuit as shown in Figure 5-5. The amplitude must be greater than 300mV peak to peak. The component values pro-
vided in Figure 5-5 are for example only. The actual values should be selected to satisfy system requirements.
The REFCLK amplitude must comply with the signal amplitudes shown in Ta bl e 4- 4 and the duty cycle in Tab le 4- 2.
FIGURE 5-4: ULPI OUTPUT CLOCK MODE
FIGURE 5-5: EXAMPLE OF CIRCUIT USED TO SHIFT A REFERENCE CLOCK COMMON-
MODE VOLTAGE LEVEL
CLKOUT
REFCLK
~
~
~
~
PHY
From PLL
Link
ULPI Clk In
Resonator
Crystal
and Caps
- or -
XO
C
LOAD
Internal
Oscillator
To PLL
Clock
47k 47k
0.1uF
VDD18
To REFCLK pin