Datasheet

USB3320
DS00001792E-page 20  2014-2016 Microchip Technology Inc.
The system must not drive voltage on the CLKOUT pin following POR or hardware reset that exceeds the value of
V
IH_ED
provided in Table 4- 4.
5.4.1.1 ULPI Input Clock Mode (60MHz REFCLK Mode)
When using ULPI Input Clock Mode, the Link must supply the 60MHz ULPI clock to the USB3320. As shown in Figure 5-
2, the 60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDDIO. A simplified
schematic using the ULPI Input Clock Mode is shown in Figure 8-2.
After the PLL has locked to the correct frequency, the USB3320 will de-assert DIR and the Link can begin using the
ULPI interface. The USB3320 is ensured to start the clock within the time specified in Table 4-2. For Host applications,
the ULPI AutoResume bit should be enabled. This is described in Section 6.2.4.4.
REFSEL[2], REFSEL[1] and REFSEL[0] should all be tied to VDDIO for ULPI Input Clock Mode.
5.4.1.2 ULPI Output Clock
When using ULPI Output Clock Mode, the USB3320 generates the 60MHz ULPI clock used by the Link. The frequency
of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Tab le 5- 10 . As shown
in Figure 5-3, the CLKOUT pin sources the 60MHz ULPI clock to the Link.
FIGURE 5-2: CONFIGURING THE USB332X FOR ULPI INPUT CLOCK MODE (60 MHZ)
FIGURE 5-3: CONFIGURING THE USB332X FOR ULPI OUTPUT CLOCK MODE
CLKOUT
REFCLK
~
~
~
~
PHY
Clock
Source
To PLL
Link
ULPI Clk Out
Reference Clk In
VDDIO
CLKOUT
REFCLK
~
~
~
~
PHY
From PLL
Clock
Source
To PLL
Link
ULPI Clk In