Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 19
USB3320
Note 1: This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.
2: USB3320 does not support operation as an upstream hub port. See Section 6.2.4.3, "UTMI+ Level 3".
Note 5-1 The transceiver operation is not ensured in a combination that is not defined.
The USB3320 uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table 4-5.
5.3 Bias Generator
This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the
analog circuits. This block requires an external 8.06K, 1% tolerance, reference resistor connected from RBIAS to
ground. This resistor should be placed as close as possible to the USB3320 to minimize the trace length. The nominal
voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80W of power.
5.4 Integrated Low Jitter PLL
The USB3320 uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS
USB signal quality. This clock is used by the transceiver during both transmit and receive. The USB3320 PLL requires
an accurate frequency reference to be driven on the REFCLK pin.
5.4.1 REFCLK MODE SELECTION
The USB3320 is designed to operate in one of two available modes as shown in Ta bl e 5- 2. In the first mode, a 60MHz
ULPI clock is driven on the REFCLK pin as described in Section 5.4.1.1. In the second mode, the USB3320 generates
the ULPI clock as described in Section 5.4.1.2. When using the second mode, the frequency of the reference clock is
configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Section 5.10.
During start-up, the USB3320 monitors the CLKOUT pin to determine which mode has been configured as described
in Section 5.4.1.1.
Peripheral Test J/Test K 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b
OTG device, Peripheral Chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b
OTG device, Peripheral HS 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b
OTG device, Peripheral FS 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b
OTG device, Peripheral HS/FS Suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b
OTG device, Peripheral HS/FS Resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b
OTG device, Peripheral Test J/Test K 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b
Any combination not defined above Note 5-
1
0b 0b 0b 0b 0b
TABLE 5-2: REFCLK MODES
Mode
REFCLK
Frequency
ULPI Clock Description
ULPI Input Clock Mode 60Mhz Sourced by Link, driven on the REFCLK pin
ULPI Output Clock
Mode
Table 5-10 Sourced by USB3320 at the CLKOUT pin
TABLE 5-1: DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED)
Signaling Mode
ULPI Register Settings
USB3320 Termination Resistor
Settings
XCVRSELECT[1:0]
TERMSELECT
OPMODE[1:0]
DPPULLDOWN
DMPULLDOWN
RPU_DP_EN
RPU_DM_EN
RPD_DP_EN
RPD_DM_EN
HSTERM_EN