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Table Of Contents
2014-2016 Microchip Technology Inc. DS00001792E-page 17
USB3320
5.0 ARCHITECTURE OVERVIEW
The USB3320 consists of the blocks shown in the diagram below. All pull-up resistors shown in this diagram are con-
nected internally to the VDD33 pin.
5.1 ULPI Digital Operation and Interface
This section of the USB3320 is covered in detail in Section 6.0, "ULPI Operation".
5.2 USB 2.0 Hi-Speed Transceiver
The blocks in the lower left-hand corner of Figure 5.1 interface to the DP/DM pins.
5.2.1 USB TRANSCEIVER
The USB3320 includes the receivers and transmitters that are compliant to the Universal Serial Bus Specification Rev
2.0. The DP/DM signals in the USB cable connect directly to the receivers and transmitters.
The RX block consists of a differential receiver for HS and separate receivers for FS/LS mode. Depending on the mode,
the selected receiver provides the serial data stream through the multiplexer to the RX Logic block. For HS mode sup-
port, the HS RX block contains a squelch circuit to insure that noise is not interpreted as data. The RX block also
includes a single-ended receiver on each of the data lines to determine the correct FS linestate.
Data from the TX Logic block is encoded, bit stuffed, serialized and transmitted onto the USB cable by the TX block.
Separate differential FS/LS and HS transmitters are included to support all modes.
The USB3320 TX block meets the HS signaling level requirements in the USB 2.0 Specification when the PCB traces
from the DP and DM pins to the USB connector have very little loss. In some systems, it may be desirable to compensate
for loss by adjusting the HS transmitter amplitude. The Boost bits in the HS TX Boost register may be configured to
adjust the HS transmitter amplitude at the DP and DM pins.
FIGURE 5-1: USB3320 INTERNAL BLOCK DIAGRAM