Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 13
USB3320
Note 4-5 The resistor value follows the 27% Resistor ECN published by the USB-IF.
Note 4-6 The values shown are valid when the USB RegOutput bits in the USB IO & Power Management
register are set to the default value.
Note 4-7 An automatic waiver up to 200mV is granted to accommodate system-level elements such as
measurement/test fixtures, captive cables, EMI components, and ESD suppression.
Pull-dn Resistor Impedance R
PD
Note 4-5 14.25 16.9 20 kΩ
Weak Pull-up Resistor
Impedance
R
CD
Configured by bits 4 and 5
in USB IO & Power
Management register.
128 170 212 kΩ
HS FUNCTIONALITY
Input levels
HS Differential Input Sensitivity V
DIHS
| V(DP) - V(DM) | 100 mV
HS Data Signaling Common
Mode Voltage Range
V
CMHS
-50 500 mV
High-Speed Squelch Detection
Threshold (Differential Signal
Amplitude)
V
HSSQ
Note 4-7 100 150 mV
Output Levels
Hi-Speed Low Level
Output Voltage (DP/DM
referenced to GND)
V
HSOL
45Ω load -10 10 mV
Hi-Speed High Level
Output Voltage (DP/DM
referenced to GND)
V
HSOH
45Ω load 360 440 mV
Hi-Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)
V
OLHS
45Ω load -10 10 mV
Chirp-J Output Voltage
(Differential)
V
CHIRPJ
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
700 1100 mV
Chirp-K Output Voltage
(Differential)
V
CHIRPK
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
-900 -500 mV
Leakage Current
OFF-State Leakage Current I
LZ
±10 uA
Port Capacitance
Transceiver Input Capacitance C
IN
Pin to GND 5 10 pF
TABLE 4-5: DC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (CONTINUED)
Parameter Symbol Condition MIN TYP MAX Units