Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service

USB3320
DS00001792E-page 12 2014-2016 Microchip Technology Inc.
4.4 Digital IO Pins
4.5 DC Characteristics: Analog I/O Pins
TABLE 4-4: DIGITAL IO CHARACTERISTICS: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] &
REFCLK PINS
Parameter Symbol Condition MIN TYP MAX Units
Low-Level Input Voltage V
IL
V
SS
0.4 *
V
DDIO
V
High-Level Input Voltage V
IH
0.68 *
V
DDIO
V
DDIO
V
High-Level Input Voltage
REFCLK only
V
IH
0.68 *
V
DD18
V
DD33
V
Low-Level Output Voltage V
OL
I
OL
= 8mA 0.4 V
High-Level Output Voltage V
OH
I
OH
= -8mA V
DDIO
-
0.4
V
High-Level Output Voltage
CPEN Only
V
OH
I
OH
= -8mA V
DD33
-
0.4
V
Input Leakage Current I
LI
V
DD33
-
0.4
±10 uA
Pin Capacitance Cpin 4 pF
STP pull-up resistance R
STP
InterfaceProtectDisable = 0 55 67 77 kΩ
DATA[7:0] pull-dn resistance R
DATA_PD
ULPI Synchronous Mode 55 67 77 kΩ
CLKOUT External Drive V
IH_ED
At start-up or following reset 0.4 *
V
DDIO
V
TABLE 4-5: DC CHARACTERISTICS: ANALOG I/O PINS (DP/DM)
Parameter Symbol Condition MIN TYP MAX Units
LS/FS FUNCTIONALITY
Input levels
Differential Receiver Input
Sensitivity
V
DIFS
| V(DP) - V(DM) | 0.2 V
Differential Receiver
Common-Mode Voltage
V
CMFS
0.8 2.5 V
Single-Ended Receiver Low
Level Input Voltage
V
ILSE
Note 4-6 0.8 V
Single-Ended Receiver High
Level Input Voltage
V
IHSE
Note 4-6 2.0 V
Single-Ended Receiver
Hysteresis
V
HYSSE
0.050 0.150 V
Output Levels
Low Level Output Voltage V
FSOL
Pull-up resistor on DP;
R
L
= 1.5kΩ to V
DD33
0.3 V
High Level Output Voltage V
FSOH
Pull-down resistor on DP,
DM; Note 4-6
R
L
= 15kΩ to GND
2.8 3.6 V
Termination
Driver Output Impedance for
HS and FS
Z
HSDRV
Steady state drive 40.5 45 49.5 Ω
Input Impedance Z
INP
RX, RPU, RPD disabled 1.0 MΩ
Pull-up Resistor Impedance R
PU
Bus Idle, Note 4-5 0.900 1.24 1.575 kΩ
Pull-up Resistor Impedance R
PU
Device Receiving, Note 4-5 1.425 2.26 3.09 kΩ