Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 11
USB3320
4.2 Clock Specifications
Note 4-3 The Suspend Recovery Time is measured from the start of the REFCLK to when the USB3320 de-
asserts DIR.
4.3 ULPI Interface Timing
Note 4-4 REFCLK does not need to be aligned in any way to the ULPI signals.
TABLE 4-2: ULPI CLOCK SPECIFICATIONS
Parameter Symbol Condition MIN TYP MAX Units
Suspend Recovery Time
Note 4-3
T
START
26MHz REFCLK 1.03 2.28 ms
12MHz REFCLK 2.24 3.49 ms
52MHz REFCLK 0.52 1.77 ms
24MHz REFCLK 1.12 2.37 ms
19.2MHz REFCLK 1.40 2.65 ms
27MHz REFCLK 1.00 2.25 ms
38.4MHz REFCLK 0.70 1.95 ms
13MHz REFCLK 2.07 3.32 ms
PHY Preparation Time T
PREP
60MHz REFCLK
ULPI Input Clock Mode
0.40.450.5ms
CLKOUT Duty Cycle DC
CLKOUT
ULPI Input Clock Mode 45 55 %
REFCLK Duty Cycle DC
REFCLK
20 80 %
REFCLK Frequency Accuracy F
REFCLK
-500 +500 PPM
Note: The USB3320 uses the AutoResume feature, Section 6.2.4.4, to allow a host start-up time of less than
1ms.
TABLE 4-3: ULPI INTERFACE TIMING
Parameter Symbol Condition MIN MAX Units
60MHz ULPI Output Clock Note 4-4
Setup time (STP, data in) T
SC
, T
SD
Model-specific REFCLK 5.0 ns
Hold time (STP, data in) T
HC
, T
HD
Model-specific REFCLK 0.0 ns
Output delay (control out, 8-bit data out) T
DC
, T
DD
Model-specific REFCLK 1.0 3.5 ns
60MHz ULPI Input Clock
Setup time (STP, data in) T
SC
, T
SD
60MHz REFCLK 1.5 ns
Hold time (STP, data in) T
HC
, T
HD
60MHz REFCLK -0.5 ns
Output delay (control out, 8-bit data out) T
DC
, T
DD
60Mhz REFCLK 1.5 6.0 ns
Note: V
DD18
= 1.6 to 2.0V; V
SS
= 0V; T
A
= -40C to +85C.