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 2014-2016 Microchip Technology Inc. DS00001792E-page 1

Features

• Integrated ESD protection circuits

- Up to ±15kV IEC Air Discharge without exter-

nal devices

• Over-Voltage Protection circuit (OVP) protects the

VBUS pin from continuous DC voltages up to 30V

• Integrated USB Switch

- No degradation of Hi-Speed electrical char-

acteristics

- Allows single USB port of connection by pro-

viding switching function for:

–Battery charging

–Stereo and mono/mic audio

–USB Full-Speed/Low-Speed data

•flexPWR

Technology

- Low current design ideal for battery powered

applications

- “Sleep” mode tri-states all ULPI pins and

places the part in a low current state

- 1.8V to 3.3V IO Voltage (±10%)

• Integrated battery to 3.3V regulator

- 2.2uF bypass capacitor

- 100mV dropout voltage

• “Wrapper-less” design for optimal timing perfor-

mance and design ease

- Low Latency Hi-Speed Receiver (43 Hi-

Speed clocks Max) allows use of legacy

UTMI Links with a ULPI bridge

• Selectable Reference Clock Frequency

- Frequencies: 12, 13, 19.2, 24, 26, 27, 38.4,

52 or 60MHz - pin selectable

• External Reference Clock operation available

- ULPI Input Clock Mode (60MHz sourced by

Link)

- 0 to 3.6V input drive tolerant

- Able to accept “noisy” clock sources as refer-

ence to internal, low-jitter PLL

• Internal Oscillator operation available

• This mode requires external Quartz Crystal or

Ceramic Resonator

• Smart detection circuits allow identification of

USB charger, headset, or data cable insertion

• Includes full support for the optional On-The-Go

(OTG) protocol detailed in the On-The-Go Sup-

plement Revision 2.0 specification

• Supports Headset Audio Mode

• Supports the OTG Host Negotiation Protocol

(HNP) and Session Request Protocol (SRP)

• UART mode for non-USB serial data transfers

• Internal 5V cable short-circuit protection of ID, DP

and DM lines to VBUS or ground

• Industrial Operating Temperature -40C to +85C

• 32-pin, QFN RoHS Compliant Package

(5 x 5 x 0.90 mm height)

Applications

The USB3320 is targeted for any application where a

Hi-Speed USB connection is desired and when board

space, power, and interface pins must be minimized.

The USB3320 is well suited for:

• Networking

• Audio Video

•Medical

• Industrial Computers

• Printers

• Repeaters

• Communication

USB3320

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI

Transceiver

Summary of content (71 pages)

PAGE 1
USB3320 Highly Integrated Full Featured Hi-Speed USB 2.
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USB3320 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com.
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USB3320 Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 USB3320 Pin Locations and Definitions ......................................................................................................................................... 6 3.0 Limiting Values ...................................................................................
PAGE 4
USB3320 1.0 INTRODUCTION 1.1 General Description The Microchip USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution and is an excellent match for a wide variety of products. The frequency of the reference clock is user selectable. The USB3320 includes an internal oscillator that may be used with either a quartz crystal or a ceramic resonator. Alternatively, the crystal input can be driven by an external clock oscillator.
PAGE 5
USB3320 The USB3320 includes an integrated 3.3V Low Drop Out (LDO) regulator that may optionally be used to generate 3.3V from power applied at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout voltage is less than 100mV which allows the transceiver to continue USB signaling when the voltage on VBAT drops to 3.1V. The USB transceiver will continue to operate at lower voltages, although some parameters may be outside the limits of the USB specifications.
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USB3320 2.0 USB3320 PIN LOCATIONS AND DEFINITIONS 2.1 USB3320 Pin Locations and Descriptions 2.1.1 PACKAGE DIAGRAM WITH PIN LOCATIONS The illustration below is viewed from the top of the package.
PAGE 7
USB3320 TABLE 2-1: USB3320 PIN DESCRIPTION (CONTINUED) Pin Name Direction/ Type Active Level 4 DATA[1] I/O, CMOS N/A ULPI bi-directional data bus. 5 DATA[2] I/O, CMOS N/A ULPI bi-directional data bus. 6 DATA[3] I/O, CMOS N/A ULPI bi-directional data bus. 7 DATA[4] I/O, CMOS N/A ULPI bi-directional data bus. 8 REFSEL[0] Input, CMOS N/A This signal, along with REFSEL[1] and REFSEL[2] selects one of the available reference frequencies as defined in Table 5-10.
PAGE 8
USB3320 TABLE 2-1: USB3320 PIN DESCRIPTION (CONTINUED) Pin Name Direction/ Type Active Level 22 VBUS I/O, Analog N/A This pin connects to an external resistor (RVBUS) connected to the VBUS pin of the USB cable. This pin is used for the VBUS comparator inputs and for VBUS pulsing during session request protocol. See Table 5-7, "Required RVBUS Resistor Value". 23 ID Input, Analog N/A ID pin of the USB cable. For applications not using ID this pin can be connected to VDD33.
PAGE 9
USB3320 3.0 LIMITING VALUES 3.1 Absolute Maximum Ratings TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Parameter Symbol VBUS, VBAT, ID, CPEN, DP, DM, SPK_L, and SPK_R voltage to GND VMAX_5V Maximum VDD18 voltage to Ground VMAX_18V Maximum VDDIO voltage to Ground VMAX_IOV Maximum VDDIO voltage to Ground VMAX_IOV Maximum VDD33 voltage to Ground Maximum I/O voltage to Ground Condition TYP MAX Units -0.5 +6.0 V -0.5 2.5 V VDD18 = VDD18 -0.5 4.0 V VDD18 = 0V -0.5 0.7 V VMAX_33V -0.5 4.
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USB3320 4.0 ELECTRICAL CHARACTERISTICS The following conditions are assumed unless otherwise specified: VVBAT = 3.1 to 5.5V; VDD18 = 1.6 to 2.0V; VDDIO = 1.6 to 2.0V; VSS = 0V; TA = -40C to +85C The current for 3.3V circuits is sourced at the VBAT pin, except when using an external 3.3V supply as shown in Figure 5-7. 4.
PAGE 11
USB3320 4.2 Clock Specifications TABLE 4-2: ULPI CLOCK SPECIFICATIONS Parameter Suspend Recovery Time Note 4-3 Symbol Condition TSTART MIN TYP MAX Units 26MHz REFCLK 1.03 2.28 ms 12MHz REFCLK 2.24 3.49 ms 52MHz REFCLK 0.52 1.77 ms 24MHz REFCLK 1.12 2.37 ms 19.2MHz REFCLK 1.40 2.65 ms 27MHz REFCLK 1.00 2.25 ms 38.4MHz REFCLK 0.70 1.95 ms 13MHz REFCLK 2.07 3.32 ms 0.45 0.5 ms PHY Preparation Time TPREP 60MHz REFCLK ULPI Input Clock Mode 0.
PAGE 12
USB3320 4.4 Digital IO Pins TABLE 4-4: DIGITAL IO CHARACTERISTICS: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] & REFCLK PINS Parameter Symbol Condition MIN TYP MAX Units Low-Level Input Voltage VIL VSS 0.4 * VDDIO V High-Level Input Voltage VIH 0.68 * VDDIO VDDIO V High-Level Input Voltage REFCLK only VIH 0.68 * VDD18 VDD33 V Low-Level Output Voltage VOL IOL = 8mA 0.4 V High-Level Output Voltage VOH IOH = -8mA VDDIO 0.
PAGE 13
USB3320 TABLE 4-5: DC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (CONTINUED) Parameter Symbol Condition MIN TYP MAX Units Pull-dn Resistor Impedance RPD Note 4-5 14.25 16.9 20 kΩ Weak Pull-up Resistor Impedance RCD Configured by bits 4 and 5 in USB IO & Power Management register.
PAGE 14
USB3320 4.6 Dynamic Characteristics: Analog I/O Pins TABLE 4-6: DYNAMIC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) Parameter Symbol Condition MIN TYP MAX Units FS Output Driver Timing FS Rise Time TFR CL = 50pF; 10 to 90% of |VOH - VOL| 4 20 ns FS Fall Time TFF CL = 50pF; 10 to 90% of |VOH - VOL| 4 20 ns Output Signal Crossover Voltage VCRS Excluding the first transition 1.3 from IDLE state 2.
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USB3320 Note 4-8 4.8 The RVPD and RVPU values include the required 1kΩ external RVBUS resistor. USB Audio Switch Characteristics TABLE 4-8: USB AUDIO SWITCH CHARACTERISTICS Parameter Symbol Condition MIN TYP MAX Minimum “ON” Resistance RON_Min 0 < Vswitch < VDD33 2.7 5 5.8 Maximum “ON” Resistance RON_Max 0 < Vswitch < VDD33 4.5 7 10 Minimum “OFF” Resistance ROFF_Min 0 < Vswitch < VDD33 1 4.
PAGE 16
USB3320 4.10 Piezoelectric Resonator for Internal Oscillator The internal oscillator may be used with an external quartz crystal or ceramic resonator as described in Section 5.4.1.2. See Table 4-11 for the recommended crystal specifications.
PAGE 17
USB3320 5.0 ARCHITECTURE OVERVIEW The USB3320 consists of the blocks shown in the diagram below. All pull-up resistors shown in this diagram are connected internally to the VDD33 pin.
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USB3320 5.2.2 TERMINATION RESISTORS The USB3320 transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes 1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω high speed termination resistors. These resistors require no tuning or trimming by the Link. The state of the resistors is determined by the operating mode of the transceiver when operating in synchronous mode.
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USB3320 DP/DM TERMINATION VS.
PAGE 20
USB3320 The system must not drive voltage on the CLKOUT pin following POR or hardware reset that exceeds the value of VIH_ED provided in Table 4-4. 5.4.1.1 ULPI Input Clock Mode (60MHz REFCLK Mode) When using ULPI Input Clock Mode, the Link must supply the 60MHz ULPI clock to the USB3320. As shown in Figure 52, the 60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDDIO. A simplified schematic using the ULPI Input Clock Mode is shown in Figure 8-2.
PAGE 21
USB3320 In this mode, the REFCLK pin may be driven at the reference clock frequency. Alternatively, the internal oscillator may be used with an external crystal or resonator as shown in Figure 5-4. An example of ULPI Output Clock Mode is shown in Figure 8-1.
PAGE 22
USB3320 5.4.3 REFCLK JITTER The USB3320 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Input Clock Mode or ULPI Output Clock Mode, the USB3320 Hi-Speed eye diagram may be degraded. The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table 4-2. 5.4.
PAGE 23
USB3320 FIGURE 5-6: POWERING THE USB3320 FROM A BATTERY ~~ VBUS RVBUS VBUS To USB Con. To OTG VBAT VDD33 COUT LDO GND PHY ~~ The USB3320 can be powered from an external 3.3V supply as shown below in Figure 5-7. When using the external supply, both the VBAT and VDD33 pins are connected together. The bypass capacitor, CBYP, is recommended when using the external supply. FIGURE 5-7: POWERING THE USB3320 FROM A 3.3V SUPPLY ~~ VBUS RVBUS VBUS To USB Con. Vdd 3.
PAGE 24
USB3320 The VBAT input must never be exposed to a voltage that exceeds VVBAT. (See Table 3-2) FIGURE 5-8: POWERING THE USB3320 FROM VBUS ~~ RVBUS VBUS VBUS To USB Con. To OTG VBAT OVP VDD33 COUT LDO GND ~~ 5.5.2 PHY POWER ON RESET (POR) The USB3320 provides a POR circuit that generates an internal reset pulse after the VDD18 supply is stable.
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USB3320 TABLE 5-3: OPERATING MODE VS. POWER SUPPLY CONFIGURATION (CONTINUED) VDD33 VDD18 RESETB 1 1 0 RESET Mode 1 1 1 Full USB operation as described in Section 6.0, "ULPI Operation". Anytime VBAT is powered per Table 3-2, the VDD33 pin will be powered up. Note: VDDIO must be powered to tri-state the ULPI interface in this configuration. Note 5-2 5.5.4 Operating Modes Available START-UP The power on default state of the USB3320 is ULPI Synchronous mode.
PAGE 26
USB3320 5.6 USB On-The-Go (OTG) The USB3320 provides full support for USB OTG protocol. OTG allows the USB3320 to be dynamically configured as a host or device depending on the type of cable inserted into the receptacle. When the Micro-A plug of a cable is inserted into the Micro-AB receptacle, the USB device becomes the A-device. When a Micro-B plug is inserted, the device becomes the B-device. The OTG A-device behaves similar to a Host while the B-device behaves similar to a peripheral.
PAGE 27
USB3320 5.6.1.2 Measuring ID Resistance to Ground The Link can used the integrated resistance measurement capabilities to determine the value of an ID resistance to ground. Table 5-4 lists the valid values of resistance, to ground, that the USB3320 can detect.
PAGE 28
USB3320 5.6.2 VBUS MONITOR AND PULSING The USB3320 includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and SessEnd comparators shown in Figure 5-11 are fully integrated into the USB3320. These comparators are used to monitor changes in the VBUS voltage, and the state of each comparator can be read from the USB Interrupt Status register. The VbusVld comparator is used by the Link, when configured as an A device, to ensure that the VBUS voltage on the cable is valid.
PAGE 29
USB3320 rupt Enable Rising and USB Interrupt Enable Falling registers. When the interrupts are disabled, the SessVld comparator is not disabled and its state can be read in the USB Interrupt Status register. The SessVld comparator trip point is detailed in Table 4-7. Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-Device Session Valid comparator. The USB3320 transceiver combines the two comparators into one and uses the narrower threshold range. 5.6.2.
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USB3320 5.6.2.6 VBUS Overvoltage Protection The USB3320 provides an integrated overvoltage protection circuit to protect the VBUS pin from excessive voltages that may be present at the USB connector. The overvoltage protection circuit works with an external resistor (RVBUS) by drawing current across the resistor to reduce the voltage at the VBUS pin. When voltage at the VBUS pin exceeds 5.5V, the Overvoltage Protection block will sink current to ground until VBUS is below 5.5V.
PAGE 31
USB3320 FIGURE 5-12: USB3320 DRIVES CONTROL SIGNAL (CPEN) TO EXTERNAL VBUS SWITCH USB Transceiver CPEN VBUS Switch EN 5V IN +5V VBUS Supply RVBUS OUT Link Controller DrvVbus DrvVbusExternal VBUS ULPI CPEN Logic USB Connector VBUS DM DP 5.7 DM DP USB UART Support The USB3320 provides support for the USB UART interface as detailed in the ULPI specification and the former CEA936A specification. The USB3320 can be placed in UART Mode using the method described in Section 6.
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USB3320 During normal USB operation the switches are off. When USB Audio is desired the switches can be turned “on” by enabling the SpkLeftEn, SpkRightEn, or MicEn bits in the Carkit Control register as described in Section 6.5.2. These bits are disabled by default. The USB Audio Switches can also be enabled by asserting the RESETB pin or removing the voltage at VDD18 as shown in Table 5-9. While using the USB switches, VDD18 is not required, but 3.3V must be present at VDD33. The integrated 3.
PAGE 33
USB3320 6.0 ULPI OPERATION 6.1 Overview The USB3320 uses the industry standard ULPI digital interface to facilitate communication between the USB Transceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB Transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals.
PAGE 34
USB3320 RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 high speed clocks. USB3320 uses a low latency high speed receiver path to lower the RxEndDelay to 43 high speed clocks. This low latency design gives the Link more cycles to make decisions and reduces the Link complexity. This is the result of the “wrapper less” architecture of the USB3320. This low RxEndDelay should allow legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface.
PAGE 35
USB3320 6.1.2 ULPI INTERFACE TIMING IN SYNCHRONOUS MODE The control and data timing relationships are given in Figure 6-2 and Table 4-3. All timing is relative to the rising clock edge of the 60MHz ULPI Clock. FIGURE 6-2: ULPI SINGLE DATA RATE TIMING DIAGRAM IN SYNCHRONOUS MODE 60MHz ULPI CLK TSC THC Control In STP TSD THD Data In DATA[7:0] TDC TDC Control Out DIR, NXT TDD Data Out DATA[7:0] 6.2 ULPI Register Access A command from the Link begins a ULPI transfer from the Link to the USB3320.
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USB3320 6.2.1 ULPI REGISTER WRITE A ULPI register write operation is given in Figure 6-3. The TXD command with a register write DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the TXD CMD byte.
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USB3320 FIGURE 6-4: ULPI EXTENDED REGISTER WRITE IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] TXD CMD (extended reg write) Idle Extended address Reg Data[n] Idle DIR STP NXT ULPI Register 6.2.2 Reg Data [n-1] Reg Data [n] ULPI REGISTER READ A ULPI register read operation is given in Figure 6-5. The Link drives a TXD CMD byte with DATA[7:6] = 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address.
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USB3320 At T0, the Link will place the TXD CMD on the data bus. At T2, the transceiver will bring NXT high, signaling the Link it is ready to accept the data transfer. At T3, the transceiver reads the TXD CMD, determines it is a register read, and asserts DIR to gain control of the bus. The transceiver will also de-assert NXT. At T4, the bus ownership has transferred back to the transceiver and the transceiver drives the requested register onto the data bus.
PAGE 39
USB3320 If an RXCMD event occurs during a USB transmit, the RXCMD is blocked until STP de-asserts at the end of the transmit. The RXCMD contains the status that is current at the time the RXCMD is sent.
PAGE 40
USB3320 6.2.4.1 High Speed Long EOP When operating as a Hi-Speed host, the USB3320 will automatically generate a 40 bit long End of Packet (EOP) after a SOF PID (A5h). The USB3320 determines when to send the 40-bit long EOP by decoding the ULPI TXD CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the DpPulldown and DmPulldown bits in the OTG Control register are asserted. The Hi-Speed 40-bit long EOP is used to detect a disconnect in high speed mode.
PAGE 41
USB3320 FIGURE 6-7: ULPI TRANSMIT IN SYNCHRONOUS MODE CLK DATA[7:0] Idle TXD CMD (USB tx) D0 D1 D2 D3 IDLE Turn Around RXD CMD Turn Around DIR NXT STP DP/DM SE0 !SQUELCH SE0 During transmit the transceiver will use NXT to control the rate of data flow into the transceiver. If the USB3320 pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until NXT is asserted.
PAGE 42
USB3320 FIGURE 6-8: ULPI RECEIVE IN SYNCHRONOUS MODE CLK DATA[7:0] Idle Turn around Rxd Cmd PID D1 Rxd Cmd D2 Turn around DIR STP NXT In Figure 6-8 the transceiver asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link.
PAGE 43
USB3320 stops data transmissions and enters Full-Speed mode with 15KΩ pull-down resistors on DP and DM. The suspended device goes to Full-Speed mode with a pull-up on DP. Both the host and device remain in this state until one of them drives DM high (this is called a resume). FIGURE 6-9: ENTERING LOW POWER MODE FROM SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] TXD CMD (reg write) Idle Reg Data[n] Idle Turn Around ...
PAGE 44
USB3320 6.3.2 EXITING LOW POWER MODE To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3320 will begin its start-up procedure. After the transceiver start-up is complete, the transceiver will start the clock on CLKOUT and de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode. The transceiver will automatically set the SuspendM bit to a 1 in the Function Control register.
PAGE 45
USB3320 In some cases, a Link may be software configured and not have control of its STP pin until after the transceiver has started. In this case, the USB3320 has in internal pull-up on the STP input pad which will pull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register.
PAGE 46
USB3320 6.4.1 3PIN FS/LS SERIAL MODE Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6-5. TABLE 6-5: PIN DEFINITIONS IN 3 PIN SERIAL MODE Signal Connected To tx_enable DATA[0] IN Active High transmit enable. data DATA[1] I/O TX differential data on DP/DM when tx_enable is high. RX differential data from DP/DM when tx_enable is low. SE0 DATA[2] I/O TX SE0 on DP/DM when tx_enable is high. RX SE0_b from DP/DM when tx_enable is low.
PAGE 47
USB3320 TABLE 6-7: ULPI REGISTER PROGRAMMING EXAMPLE TO ENTER UART MODE R/W Address (HEX) Value (HEX) W 04 49 W 39 W 19 W 07 04 Description Result Configure Non-Driving mode Select FS transmit edge rates OpMode=01 XcvrSelect=01 00 Set regulator to 3.
PAGE 48
USB3320 After the USB3320 has detected the change of state on the ID pin, the RID converter can be used to determine the value of ID resistance. To start a ID resistance measurement, the RidConversionStart bit is set in the Vendor Rid Conversion register. The Link can use one of two methods to determine when the RID Conversion is complete. One method is polling the RidConversionStart bit as described in Section 7.1.3.3. The preferred method is to set the RidIntEn bit in the Vendor Rid Conversion register.
PAGE 49
USB3320 7.0 ULPI REGISTER MAP 7.1 ULPI Register Array The USB3320 Transceiver implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete USB3320 ULPI register set is shown in Table 7-1. All registers are 8 bits. This table also includes the default state of each register upon POR or de-assertion of RESETB, as described in Section 5.5.2. The RESET bit in the Function Control Register does not reset the bits of the ULPI register array.
PAGE 50
USB3320 7.1.1 ULPI REGISTER SET The following registers are used for the ULPI interface. 7.1.1.1 Vendor ID Low Address = 00h (read only) Field Name Vendor ID Low 7.1.1.2 Bit Access Default 7:0 rd 24h Bit Access Default 7:0 rd 04h Bit Access Default 7:0 rd 07h Bit Access Default 7:0 rd 00h Description Microchip Vendor ID Vendor ID High Address = 01h (read only) Field Name Vendor ID High 7.1.1.
PAGE 51
USB3320 Field Name Bit Access Default Description SuspendM 6 rd/w/s/c 1b Active low PHY suspend. When cleared the transceiver will enter Low Power Mode as detailed in Section 6.3. Automatically set when exiting Low Power Mode. Reserved 7 rd 0b Read only, 0. 7.1.1.
PAGE 52
USB3320 Field Name Bit Access Default Description DischrgVbus 3 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to ground to discharge VBUS. 0b: disconnect resistor from VBUS to ground 1b: connect resistor from VBUS to ground ChrgVbus 4 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to VDD33 to charge VBUS above the SessValid threshold.
PAGE 53
USB3320 Field Name Bit Access Default Description SessEnd Fall 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from high to low. IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from high to low. Reserved 7:5 rd 000b 7.1.1.10 Read only, 0. USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources.
PAGE 54
USB3320 7.1.1.13 Scratch Register Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) Field Name Scratch 7.1.2 Bit Access Default Description 7:0 rd/w/s/c 00h Empty register byte for testing purposes. Software can read, write, set, and clear this register and the transceiver functionality will not be affected. CARKIT CONTROL REGISTERS The following registers are used to set-up and enable the USB UART and USB Audio functions. 7.1.2.
PAGE 55
USB3320 Field Name RidIntEn Bit Access Default Description 5 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: 7:6 This register bit is or’ed with the RidIntEn bit of the Vendor Rid Conversion register described in Section 7.1.3.3. rd 00b Bit Access Default Description IdFloat 0 rd 0b Asserted when the ID pin is floating. IdPullup must be enabled. CarIntDet 1 rd 0b Not Implemented. Reads as 0b.
PAGE 56
USB3320 7.1.3 VENDOR REGISTER ACCESS The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI immediate register read / write. 7.1.3.1 HS TX Boost Address = 31h (read / write) Field Name Bit Access Default Description Reserved 4:0 rd 00000b Boost 6:5 rd/w 00b Sets the HS transmitter amplitude as described in Section 5.2.1. 00b: Nominal 01b: Enables 11.1% increased drive strength 10b: Enables 7.4% increased drive strength 11b: Enables 3.
PAGE 57
USB3320 Field Name RidIntEn Bit Access Default Description 6 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: 7 Reserved 0b Read only, 0. rd: Read Only with auto clear. Note 7-4 7.1.3.4 rd This register bit is or’ed with the RidIntEn bit of the Carkit Interrupt Status register.
PAGE 58
USB3320 8.0 APPLICATION NOTES 8.1 Application Diagram The USB3320 requires few external components as shown in the application diagrams. The USB 2.0 Specification restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, the voltage will exceed this voltage, and the USB3320 provides an integrated overvoltage protection circuit. The overvoltage protection circuit works with an external resistor (RVBUS) to lower the voltage at the VBUS pin, as described in Section 5.6.2.6.
PAGE 59
USB3320 FIGURE 8-1: USB3320 APPLICATION DIAGRAM (DEVICE, ULPI OUTPUT CLOCK MODE, 24MHZ) VDDIO Supply RVBUS must be installed to enable overvoltage protection of the VBUS pin. RVBUS 3.1-5.5V Supply The capacitor CVBUS must be installed on this side of RVBUS.
PAGE 60
USB3320 FIGURE 8-2: USB3320 APPLICATION DIAGRAM (DEVICE, ULPI INPUT CLOCK MODE, 60MHZ) VDDIO Supply RVBUS must be installed to enable overvoltage protection of the VBUS pin. 14 11 8 RVBUS 3.1-5.5V Supply The capacitor CVBUS must be installed on this side of RVBUS.
PAGE 61
USB3320 FIGURE 8-3: USB3320 APPLICATION DIAGRAM (HOST OR OTG, ULPI OUTPUT CLOCK MODE, 24MHZ) VDDIO Supply 14 11 8 VBUS Switch EN 5V IN OUT The capacitor CVBUS must be installed on this side of RVBUS. RVBUS must be installed to enable overvoltage protection of the VBUS pin. RVBUS REFSEL2 REFSEL1 REFSEL0 17 CPEN 22 VBUS 3.1-5.
PAGE 62
USB3320 8.2 Reference Designs Microchip has generated reference designs for connecting the USB3320 to SOCs with a ULPI port. Please contact the Microchip sales office for more details. 8.3 ESD Performance The USB3320 is protected from ESD strikes. By eliminating the requirement for external ESD protection devices, board space is conserved, and the board manufacturer is enabled to reduce cost. The advanced ESD structures integrated into the USB3320 protect the device whether or not it is powered up. 8.
PAGE 63
USB3320 9.0 PACKAGE INFORMATION 9.1 Package Marking Information Example 32-Lead QFN (5x5x0.85 mm) USB3320C RYYWWXXXX YYWWNNNA VCOO USB3320C A15410000 1541000A ASETW e3 PIN 1 Legend: e3 PIN 1 USB3320C R YYWW XXXX YYWWNNNA V COO e3  2014-2016 Microchip Technology Inc.
PAGE 64
USB3320 9.2 Package Details The USB3320 is offered in a compact 32 pin QFN package. 32-PIN QFN, 5X5MM BODY, 0.5MM PITCH Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging FIGURE 9-1: DS00001792E-page 64  2014-2016 Microchip Technology Inc.
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Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging USB3320 FIGURE 9-1: 32-PIN QFN, 5X5MM BODY, 0.5MM PITCH (CONTINUED)  2014-2016 Microchip Technology Inc.
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USB3320 FIGURE 9-2: QFN, 5X5 TAPING DIMENSIONS AND PART ORIENTATION A Ø1.50 4.00 0.30 Ø1.50 2.00 1.75 R0.3 MAX 5.50 12.00 B0 K0 8.00 A0 0.25 SECTION A — A A R0.25 10 mm DIRECTION OF UNREELING A0 DS00001792E-page 66 5.25 B0 5.25 K0 1.10  2014-2016 Microchip Technology Inc.
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USB3320 APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Level & Date Section/Figure/Entry Correction DS00001793E (05-31-16) Table 4-11, "USB3320 Quartz Column headings modified. Crystal Specifications" DS00001792D (04-13-16) Table 4-3, "ULPI Interface Timing" Table heading corrected: “TYP” changed to “MAX” DS00001792C (03-28-16) Table 4-3, "ULPI Interface Timing" Table heading corrected: “MAX” changed to “Units” Section 9.
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USB3320 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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USB3320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. - XXX - Package Device Device: USB3320C Temperature Range: -40C to+85C Package: EZK Tape and Reel Option: Blank TR = [X](1) Tape and Reel Option Examples: a) USB3320C-EZK b) USB3320C-EZK-TR 32-pin QFN RoHS Compliant package = Standard packaging (tray) = Tape and Reel(1) Note 1:  2014-2016 Microchip Technology Inc.
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USB3320 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.