Datasheet

USB 2.0 Hi-Speed 7-Port Hub Controller
Datasheet
Revision 2.8 (09-17-12) 38 SMSC USB2517
DATASHEET
The Hub’s SMBus implementation is a subset of the SMBus interface to the host. The device is a slave-only SMBus
device. The implementation in the device is a subset of SMBus since it only supports two protocols.
The Write Block and Read Block protocols are the only valid SMBus protocols for the Hub. The Hub responds to
other protocols as described in Section 7.3.2, "Invalid Protocol Response Behavior," on page 39. Reference the
System Management Bus Specification, Rev 1.0.
The SMBus interface is used to read and write the registers in the device. The register set is shown in Section 7.2.1,
"Internal Register Set (Common to EEPROM and SMBus)," on page 19.
7.3.1 Bus Protocols
Typical Write Block and Read Block protocols are shown below. Register accesses are performed using 7-bit slave
addressing, an 8-bit register address field, and an 8-bit data field. The shading indicates the Hub driving data on the
SMBDATA line; otherwise, host data is on the SDA/SMBDATA line.
The slave address is the unique SMBus Interface Address for the Hub that identifies it on SMBus. The register
address field is the internal address of the register to be accessed. The register data field is the data that the host
is attempting to write to the register or the contents of the register that the host is attempting to read.
Note: Data bytes are transferred MSB first (msb first).
7.3.1.1 Block Read/Write
The Block Write begins with a slave address and a write condition. After the command code, the host issues a byte
count which describes how many more bytes will follow in the message. If a slave had 20 bytes to send, the first
byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A Block Read
or Write is allowed to transfer a maximum of 32 data bytes.
Note: For the following SMBus tables:
Figure 7.1 Block Write
Block Read
A Block Read differs from a block write in that the repeated start condition exists to satisfy the I
2
C specification’s
requirement for a change in the transfer direction.
Figure 7.2 Block Read
Denotes Master-to-Slave Denotes Slave-to-Master
181
S Slave Address Register AddressWr A
17118
A
1
...
Byte Count = N
A Data byte 1 A Data byte 2
81 1 188
Data byte N A P
Block Write
A
Block Read
1
SS Slave Address Register AddressWr A
17118
A
1
Slave Address Rd A
711
81 1 188
P
181
A AAA
Byte Count = N
Data byte 1 Data byte 2 Data byte N
...