Datasheet

USB 2.0 Hi-Speed 7-Port Hub Controller
Datasheet
SMSC USB2517 15 Revision 2.8 (09-17-12)
DATASHEET
Table 5.2 USB2517 SMBUS or EEPROM Interface Behavior
TEST 19 IPD TEST pin
XNOR continuity tests all signal pins on the hub. Please contact
your SMSC representative for a detailed description of how this
test mode is enabled and utilized.
Power, Ground, No Connect
VDD18 25 VDD Core
+1.8V core power. This pin must have a 1.0
μF (or greater) ±20%
(ESR <0.1Ω) capacitor to VSS.
VDD33PLL 64
VDD 3.3 PLL Regulator Reference
+3.3V power supply for the Digital I/O. If the internal PLL 1.8V reg-
ulator is enabled, then this pin acts as the regulator input.
VDD18PLL 62 VDD PLL
+1.8V Filtered analog power for internal PLL. This pin must have
a 1.0
μF (or greater) ±20% (ESR <0.1Ω) capacitor to VSS.
VDD33 46 VDD I/O
+3.3V Digital I/O power
VDDA33 5
10
52
57
VDD Analog I/O
+3.3V Filtered analog PHY power which is shared between
adjacent ports.
VDD33CR 24 VDDIO/VDD 3.3 Core Regulator Reference
+3.3V power supply for the Digital I/O. If the internal core
regulator is enabled, then VDD33CR acts as the regulator input.
Ground VSS Slug Ground
CFG_SEL2 CFG_SEL1 CFG_SEL0 SMBUS OR EEPROM INTERFACE BEHAVIOR
0 0 0 Internal Default Configuration
 Strap Option sare Enabled
0 0 1 Configured as an SMBus slave for external download
of user-defined descriptors
 SMBus slave address is ‘0101100’
 Strap Options are Disabled
 All Settings are Controlled by Registers
0 1 0 Internal Default Configuration
 Strap Options are Enabled
 Bus Power Operation
 LED Mode = USB
01 12-Wire
I
2
C EEPROMS are supported
 Strap Options are Disabled
 All Settings are Controlled by Registers
1 0 0 Internal Default Configuration
 Strap Options are Disabled
 Dynamic Power Switching is Enabled
Table 5.1 USB2517 Pin Descriptions (continued)
SYMBOL 64 QFN
BUFFER
TYPE DESCRIPTION