Datasheet

TCN75A
DS21935A-page 16 © 2005 Microchip Technology Inc.
5.0 SERIAL COMMUNICATION
5.1 2-Wire I
2
C™ Compatible Interface
The TCN75A serial clock input (SCLK) and the bidirec-
tional Serial Data (SDA) line form a 2-wire bidirectional
serial port for communication.
The following bus protocol has been defined:
TABLE 5-1: SERIAL BUS CONVENTIONS
5.1.1 DATA TRANSFER
Data transfers are initiated by a START condition,
followed by a 7-bit device address and a 1-bit read/
write. Acknowledge (ACK) from slave confirms the
reception of each byte. Each access must be
terminated by a STOP condition.
Data transfer may be initiated when the bus is in idle.
5.1.2 MASTER/SLAVE
The bus is controlled by a master device (typically a
microcontroller) that controls the bus access and gener-
ates the START and STOP conditions. The TCN75A is
a slave device and does not control other devices in the
bus. Both master and slave devices can operate as
either transmitter or receiver. However, the master
device determines which mode is activated.
5.1.3 START/STOP CONDITION
A high-to-low transition of the SDA line (while SCLK is
high) is the START condition. All data transfers must be
preceded by a START condition from the master. If a
START condition is generated during data transfer, the
TCN75A resets and accepts the new START condition.
A low-to-high transition of the SDA line (while SCLK is
high) is the STOP condition. All data transfers must be
ended by a STOP condition from the master. If a STOP
condition is introduced during data transmission, the
TCN75A releases the bus.
5.1.4 ADDRESS BYTE
Following the START condition, the host must transmit
the address byte to the TCN75A. The address for the
TCN75A is <1001,A2,A1,A0> in binary, where the
A0, A1 and A2 bits are set externally by connecting the
corresponding pins to V
DD
<1> or GND <0>. The 7-bit
address transmitted in the serial bit stream must match
the selected address for the TCN75A to respond with an
ACK.
Bit 8 in the address byte is a read/write bit. Setting this
bit to ‘1’ commands a read operation, while ‘0’
commands a write operation.
FIGURE 5-1: Device Addressing.
5.1.5 DATA VALID
After the start condition, each bit of data in transmission
needs to be settled for time specified by t
SU-DATA
before SCLK toggles from low-to-high (refer to the
Serial Interface Timing Specification).
5.1.6 ACKNOWLEDGE (ACK)
Each receiving device, when addressed, is obliged to
generate an acknowledge bit after the reception of
each byte. The master device must generate an extra
clock pulse for ACK to be recognized.
The acknowledging device has to pull down the SDA
line for t
SU-DATA
before the low-to-high transition of
SCLK from the Master and remains pulled down for
t
H-DATA
after high-to-low transition of SCLK.
During read, the master must signal an End-of-Data
(EOD) to the slave by not generating an ACK bit once
the last bit has been clocked out of the slave. In this
case, the slave will leave the data line released to
enable the master to generate the STOP condition.
Term Description
Transmitter Device sending data to the bus
Receiver Device receiving data from the bus
Master The device that controls the serial bus,
typically a microcontroller
Slave The device addressed by the master,
such as the TCN75A
START A unique signal from master to initiate
serial interface with a slave
STOP A unique signal from the master to
terminate serial interface from a slave
Read/Write A read or write to the TCN75A registers
ACK A receiver Acknowledges (ACK) the
reception of each byte by polling the
bus
NAK A receiver Not-Acknowledges (NAK) or
releases the bus to show End-of-Data
(EOD)
Busy Communication is not possible
because the bus is in use
Not Busy The bus is in the idle state, both SDA
and SCLK remain high
Data Valid SDA must remain stable before SCLK
becomes high in order for a data bit to
be considered valid. During normal
data transfers, SDA only changes state
while SCLK is low.
123456789
SCLK
SDA
1
00
1A2A1A0
Start
Address Byte
Slave
Address
R/W
TCN75A Response
Code
Address
A
C
K