Datasheet

©2012 Silicon Storage Technology, Inc. DS25023B 06/13
15
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Figure 6: CE# Controlled Program Cycle Timing Diagram
Figure 7: Data# Polling Timing Diagram
1150 F05.0
ADDRESS A
MS-0
DQ
7-0
T
DH
T
CPH
T
DS
T
CP
T
AH
T
AS
T
CH
T
CS
WE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
CE#
T
BP
Note: A
MS
= Most significant address
A
MS
= A
16
for SST39LF/VF010, A
17
for SST39LF/VF020 and A
18
for SST39LF/VF040
1150 F06.0
ADDRESS A
MS-0
DQ
7
DD# D# D
WE#
OE#
CE#
T
OEH
T
OE
T
CE
T
OES
Note: A
MS
= Most significant address
A
MS
= A
16
for SST39LF/VF010, A
17
for SST39LF/VF020 and A
18
for SST39LF/VF040