Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet The SST39SF010A / SST39SF020A / SST39SF040 are CMOS Multi-Purpose Flash (MPF) devices manufactured with SST proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF010A / SST39SF020A / SST39SF040 write (Program or Erase) with a 4.5-5.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Product Description The SST39SF010A/020A/040 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF010A/020A/040 devices write (Program or Erase) with a 4.5-5.5V power supply.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Block Diagram X-Decoder Memory Address SuperFlash Memory Address Buffers & Latches Y-Decoder CE# OE# Control Logic I/O Buffers and Data Latches WE# DQ7 - DQ0 1147 B1.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet A4 A3 A17 WE# VDD A18 A16 A15 A12 A17 A4 WE# A5 NC A5 WE# A5 VDD 6 VDD A6 NC A6 A16 A6 NC 5 A16 A7 A15 A7 A15 A7 A12 SST39SF020A SST39SF010A SST39SF040 SST39SF020A SST39SF010A A12 SST39SF040 Pin Assignment 4 3 2 1 32 31 30 29 SST39SF010A SST39SF020A SST39SF040 A14 A14 28 A13 A13 A13 7 27 A8 A8 A8 A4 8 26 A9 A9 A9 A3 A3 9 25 A11 A11 A11 A2 A2 A
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet SST39SF040 SST39SF020A A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 SST39SF010A A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 SST39SF010A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up SST39SF020A OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Table 1: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Write Operation Status Detection The SST39SF010A/020A/040 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Software Data Protection (SDP) The SST39SF010A/020A/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Operations Table 3: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN X1 Sector address, XXH for Chip-Erase High Z X Erase VIL VIH VIL Standby VIH X X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.3 25022 1.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Table 7: DC Operating Characteristics VDD = 4.5-5.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet AC Characteristics Table 11: Read Cycle Timing Parameters VDD = 4.5-5.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TRC TAA ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TOH TCLZ DQ7-0 HIGH-Z TCHZ DATA VALID DATA VALID HIGH-Z 1147 F03.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH 2AAA 5555 ADDR TDH TCP CE# TDS TCPH TAS OE# TCH WE# TCS DQ7-0 AA SW0 55 A0 SW1 SW2 DATA BYTE (ADDR/DATA) 1147 F05.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet ADDRESS AMS-0 TCE CE# TOEH TOES TOE OE# WE# Note DQ6 TWO READ CYCLES WITH SAME OUTPUTS 1147 F07.1 Note: Toggled bit output is always high first.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ7-0 AA SW0 55 80 AA 55 10 SW1 SW2 SW3 SW4 SW5 1147 F17.1 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) SAXX = Sector Address Toggled bit output is always high first.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 5555 DQ7-0 2AAA 5555 AA 55 F0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 1147 F10.0 Figure 13:Software ID Exit and Reset VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1147 F11.1 AC test inputs are driven at VIHT (3.0V) for a logic “1” and VILT (0V) for a logic “0”. Measurement reference points for inputs and outputs are VIT (1.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1147 F13.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Internal Timer Toggle Bit Data# Polling Byte Program/Erase Initiated Byte Program/Erase Initiated Byte Program/Erase Initiated Read byte Read DQ7 Wait TBP, TSCE, or TSE Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1147 F14.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: 30H
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Product Ordering Information SST 39 SF XX XX 010A - XXXX - 70 - 4C - NHE XX - XX - XXX Environmental Attribute E1 = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns 70 = 70 ns Version A = Spe
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Valid combinations for SST39SF010A SST39SF010A-55-4C-NHE SST39SF010A-55-4C-WHE SST39SF010A-70-4C-NHE SST39SF010A-70-4C-WHE SST39SF010A-55-4I-NHE SST39SF010A-55-4I-WHE SST39SF010A-70-4I-NHE SST39SF010A-70-4I-WHE SST39SF010A-70-4C-PHE Valid combinations for SST39SF020A SST39SF020A-55-4C-NHE SST39SF020A-55-4C-WHE SST39SF020A-70-4C-NHE SST39SF020A-70-4C-WHE SST39SF020A-55-4I-NHE SST39SF020A-55-4I-WHE S
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Packaging Diagrams TOP VIEW Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447 2 1 32 SIDE VIEW .112 .106 .020 R. .029 x 30° MAX. .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0°- 5° 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 32-tsop-WH-7 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet 32 CL Pin #1 Identifier 1 1.655 1.645 .075 .065 7° 4 PLCS. Base Plane Seating Plane .625 .600 .550 .530 .200 .170 .050 .015 .080 .070 .065 .045 .022 .016 .100 BSC .150 .120 0° 15° .012 .008 .600 BSC Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Table 13: Revision History Revision Description Date 02 • 2002 Data Book May 2002 03 • • • Changes to Table 7 on page 12 Added footnote for MPF power usage and Typical conditions Clarified the Test Conditions for Power Supply Current and Read parameters Clarified IDD Write to be Program and Erase Mar 2003 Document status changed from “Preliminary Specification” to “Data Sheet” Changed IDD Program and E
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet ISBN:978-1-5224-0456-9 © 2016 Microchip Technology Inc. SST, Silicon Storage Technology, the SST logo, SuperFlash, and MTP are registered trademarks of Microchip Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Microchip Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners.