Datasheet

SST25VF080B
DS20005045C-page 8  2015 Microchip Technology Inc.
4.4.1 READ (25 MHz)
The Read instruction, 03H, supports up to 25 MHz
Read. The device outputs the data starting from the
specified address location. The data output stream is
continuous through all addresses until terminated by a
low to high transition on CE#. The internal address
pointer will automatically increment until the highest
memory address is reached. Once the highest memory
address is reached, the address pointer will automati-
cally increment to the beginning (wrap-around) of the
address space. Once the data from address location
FFFFFH has been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A23-A0].
CE# must remain active low for the duration of the
Read cycle. See Figure 4-3 for the Read sequence.
FIGURE 4-3: READ SEQUENCE
4.4.2 HIGH-SPEED-READ (66 MHz)
1
The High-Speed-Read instruction, supporting up to
66 MHz Read, is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A23-A0] and a
dummy byte. CE# must remain active low for the dura-
tion of the High-Speed-Read cycle. See Figure 4-4 for
the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location FFFFFH
has been read, the next output will be from address
location 00000H.
FIGURE 4-4: HIGH-SPEED-READ SEQUENCE
1296 ReadSeq_0.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
03
HIGH IMPEDANCE
15 16
23
24
31
32
39
40
7047 48 55 56 63 64
N+2 N+3 N+4N N+1
D
OUT
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
1.66 MHz operations occur under the conditions specified in
Table 5-6 on page 19.
1296 HSRdSeq.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 39 40
47 48 55 56 63 64
N+2 N+3 N+4
N
N+1
X
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
80
71 72
D
OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
IL
or V
IH
)