Datasheet

SST25VF080B
DS20005045C-page 14 2015 Microchip Technology Inc.
4.4.9 CHIP-ERASE
The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction will be ignored if any
of the memory area is protected. Prior to any Write oper-
ation, the Write-Enable (WREN) instruction must be exe-
cuted. CE# must remain active low for the duration of
the Chip-Erase instruction sequence. The Chip-Erase
instruction is initiated by executing an 8-bit command,
60H or C7H. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait T
CE
for the completion of the
internal self-timed Chip-Erase cycle. See Figure 4-13
for the Chip-Erase sequence.
FIGURE 4-13: CHIP-ERASE SEQUENCE
4.4.10 READ-STATUS-REGISTER (RDSR)
The Read-Status-Register (RDSR) instruction allows
reading of the status register. The status register may
be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in prog-
ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is termi-
nated by a low to high transition of the CE#. See Figure
4-14 for the RDSR instruction sequence.
FIGURE 4-14: READ-STATUS-REGISTER (RDSR) SEQUENCE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1296 RDSRseq.0
MODE 3
SCK
SI
SO
CE#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05
MODE 0
HIGH IMPEDANCE
Status
Register Out
MSB
MSB