Datasheet

SST25VF016B

DS20005044C-page 14  2015 Microchip Technology Inc.

FIGURE 4-12: 64-KBYTE BLOCK-ERASE SEQUENCE

4.4.9 CHIP-ERASE

The Chip-Erase instruction clears all bits in the device

to FFH. A Chip-Erase instruction will be ignored if any

of the memory area is protected. Prior to any Write oper-

ation, the Write-Enable (WREN) instruction must be exe-

cuted. CE# must remain active low for the duration of

the Chip-Erase instruction sequence. The Chip-Erase

instruction is initiated by executing an 8-bit command,

60H or C7H. CE# must be driven high before the instruction

is executed. The user may poll the Busy bit in the software

status register or wait T

for the completion of the

internal self-timed Chip-Erase cycle. See Figure 4-13

for the Chip-Erase sequence.

FIGURE 4-13: CHIP-ERASE SEQUENCE

CE#

SCK

ADDR

012345678

ADDR ADDR

HIGH IMPEDANCE

15 16

MODE 0

MODE 3

1271 63KBlkEr.0

MSB MSB

CE#

SCK

01234567

60 or C7

HIGH IMPEDANCE

MODE 0

MODE 3

1271 ChEr.0

MSB