Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 75
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
6
Peripheral Set 2:
SPI1-SPI6
I2C1-I2C5
UART1-UART6
PMP
SBT6REG0 R 0x1F820000 R 64 KB
— 0 SBT6RD0 R/W
(1)
SBT6WR0 R/W
(1)
SBT6REG1 R/W R/W R/W R/W — 3 SBT6RD1 R/W
(1)
SBT6WR1 R/W
(1)
7
Peripheral Set 3:
Timer1-Timer9
IC1-IC9
OC1-OC9
ADC
Comparator 1
Comparator 2
SBT7REG0 R 0x1F840000 R 64 KB
— 0 SBT7RD0 R/W
(1)
SBT7WR0 R/W
(1)
SBT7REG1 R/W R/W R/W R/W — 3 SBT7RD1 R/W
(1)
SBT7WR1 R/W
(1)
8
Peripheral Set 4:
PORTA-PORTK
SBT8REG0 R 0x1F860000 R 64 KB
— 0 SBT8RD0 R/W
(1)
SBT8WR0 R/W
(1)
SBT8REG1 R/W R/W R/W R/W — 3 SBT8RD1 R/W
(1)
SBT8WR1 R/W
(1)
9
Peripheral Set 5:
CAN1
CAN2
Ethernet Controller
SBT9REG0 R 0x1F880000 R 64 KB
— 0 SBT9RD0 R/W
(1)
SBT9WR0 R/W
(1)
SBT9REG1 R/W R/W R/W R/W — 3 SBT9RD1 R/W
(1)
SBT9WR1 R/W
(1)
10
Peripheral Set 6:
USB
SBT10REG0 R 0x1F8E3000 R 4 KB — 0 SBT10RD0 R/W
(1)
SBT10WR0 R/W
(1)
11
External Memory via SQI1 and
SQI1 Module
SBT11REG0 R 0x30000000 R 64 MB
— 0 SBT11RD0 R/W
(1)
SBT11WR0 R/W
(1)
SBT11REG1 R 0x1F8E2000 R 4 KB — 3 SBT11RD1 R/W
(1)
SBT11WR1 R/W
(1)
12
Peripheral Set 7:
Crypto Engine
SBT12REG0 R 0x1F8E5000 R 4 KB — 0 SBT12RD0 R/W
(1)
SBT12WR0 R/W
(1)
13
Peripheral Set 8:
RNG Module
SBT13REG0 R 0x1F8E6000 R 4 KB — 0 SBT13RD0 R/W
(1)
SBT13WR0 R/W
(1)
TABLE 4-6: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED)
Target
Number
Target Description
(5)
SBTxREGy Register SBTxRDy Register SBTxWRy Register
Name
Region Base
(BASE<21:0>)
(see Note 2)
Physical
Start
Address
Region Size
(SIZE<4:0>)
(see Note 3)
Region
Size
Priority
(PRI)
Priority
Level
Name
Read
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
Name
Write
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
Legend: R = Read; R/W = Read/Write; ‘x’ in a register name = 0-13; ‘y’ in a register name = 0-8.
Note 1: Reset values for these bits are ‘0’, ‘1’, ‘1’, ‘1’, respectively.
2: The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
3: The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2
(SIZE-1)
x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
4: Refer to the Device Memory Maps (Figure 4-1 through Figure 4-4) for specific device memory sizes and start addresses.
5: See Table 4-1for information on specific target memory size and start addresses.
6: The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.