Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320B-page 74 Preliminary  2015 Microchip Technology Inc.
TABLE 4-6: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS
Target
Number
Target Description
(5)
SBTxREGy Register SBTxRDy Register SBTxWRy Register
Name
Region Base
(BASE<21:0>)
(see Note 2)
Physical
Start
Address
Region Size
(SIZE<4:0>)
(see Note 3)
Region
Size
Priority
(PRI)
Priority
Level
Name
Read
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
Name
Write
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
0
System Bus
SBT0REG0 R 0x1F8F0000 R 64 KB
— 0 SBT0RD0 R/W
(1)
SBT0WR0 R/W
(1)
SBT0REG1 R 0x1F8F8000 R 32 KB — 3 SBT0RD1 R/W
(1)
SBT0WR1 R/W
(1)
1
Flash Memory
(6)
:
Program Flash
Boot Flash
Prefetch Module
SBT1REG0 R 0x1D000000 R
(4)
R
(4)
— 0 SBT1RD0 R/W
(1)
SBT1WR0 0, 0, 0, 0
SBT1REG2 R 0x1F8E0000 R 4 KB 1 2 SBT1RD2 R/W
(1)
SBT1WR2 R/W
(1)
SBT1REG3 R/W R/W R/W R/W 1 2 SBT1RD3 R/W
(1)
SBT1WR3 0, 0, 0, 0
SBT1REG4 R/W R/W R/W R/W 1 2 SBT1RD4 R/W
(1)
SBT1WR4 0, 0, 0, 0
SBT1REG5 R/W R/W R/W R/W 1 2 SBT1RD5 R/W
(1)
SBT1WR5 0, 0, 0, 0
SBT1REG6 R/W R/W R/W R/W 1 2 SBT1RD6 R/W
(1)
SBT1WR6 0, 0, 0, 0
SBT1REG7 R/W R/W R/W R/W 0 1 SBT1RD7 R/W
(1)
SBT1WR7 0, 0, 0, 0
SBT1REG8 R/W R/W R/W R/W 0 1 SBT1RD8 R/W
(1)
SBT1WR8 0, 0, 0, 0
2
RAM Bank 1 Memory
SBT2REG0 R 0x00000000 R
(4)
R
(4)
— 0 SBT2RD0 R/W
(1)
SBT2WR0 R/W
(1)
SBT2REG1 R/W R/W R/W R/W — 3 SBT2RD1 R/W
(1)
SBT2WR1 R/W
(1)
SBT2REG2 R/W R/W R/W R/W 0 1 SBT2RD2 R/W
(1)
SBT2WR2 R/W
(1)
3
RAM Bank 2 Memory
SBT3REG0 R
(4)
R
(4)
R
(4)
R
(4)
— 0 SBT3RD0 R/W
(1)
SBT3WR0 R/W
(1)
SBT3REG1 R/W R/W R/W R/W — 3 SBT3RD1 R/W
(1)
SBT3WR1 R/W
(1)
SBT3REG2 R/W R/W R/W R/W 0 1 SBT3RD2 R/W
(1)
SBT3WR2 R/W
(1)
4
External Memory via EBI and EBI
Module
(6)
SBT4REG0 R 0x20000000 R 64 MB — 0 SBT4RD0 R/W
(1)
SBT4WR0 R/W
(1)
SBT4REG2 R 0x1F8E1000 R 4 KB 0 1 SBT4RD2 R/W
(1)
SBT4WR2 R/W
(1)
5
Peripheral Set 1:
System Control
Flash Control
DMT/WDT
RTCC
CVR
PPS Input
PPS Output
Interrupts
DMA
SBT5REG0 R 0x1F800000 R 128 KB
— 0 SBT5RD0 R/W
(1)
SBT5WR0 R/W
(1)
SBT5REG1 R/W R/W R/W R/W — 3 SBT5RD1 R/W
(1)
SBT5WR1 R/W
(1)
SBT5REG2 R/W R/W R/W R/W 0 1 SBT5RD2 R/W
(1)
SBT5WR2 R/W
(1)
Legend: R = Read; R/W = Read/Write; ‘x’ in a register name = 0-13; ‘y’ in a register name = 0-8.
Note 1: Reset values for these bits are ‘0’, ‘1’, ‘1’, ‘1’, respectively.
2: The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
3: The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2
(SIZE-1)
x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
4: Refer to the Device Memory Maps (Figure 4-1 through Figure 4-4) for specific device memory sizes and start addresses.
5: See Table 4-1for information on specific target memory size and start addresses.
6: The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.