Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 73
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
The System Bus arbitration scheme implements a non-
programmable, Least Recently Serviced (LRS) priority,
which provides Quality Of Service (QOS) for most
initiators. However, some initiators can use Fixed High
Priority (HIGH) arbitration to guarantee their access to
data.
The arbitration scheme for the available initiators is
shown in
Table 4-5.
TABLE 4-5: INITIATOR ID AND QOS
4.3 Permission Access and System
Bus Registers
The System Bus on PIC32MZ EF family of
microcontrollers provides access control capabilities
for the transaction initiators on the System Bus.
The System Bus divides the entire memory space into
fourteen target regions and permits access to each
target by initiators via permission groups. Four
Permission Groups (0 through 3) can be assigned to
each initiator. Each permission group is independent
of the others and can have exclusive or shared
access to a region.
Using the CFGPG register (see Register 34-10 in
Section 34.0 “Special Features”), Boot firmware can
assign a permission group to each initiator, which can
make requests on the System Bus.
The available targets and their regions, as well as the
associated control registers to assign protection, are
described and listed in Table 4-6.
Register 4-2 through Register 4-10 are used for setting
and controlling access permission groups and regions.
To change these registers, they must be unlocked in
hardware. The register lock is controlled by the
PGLOCK Configuration bit (CFGCON<11>). Setting
PGLOCK prevents writes to the control registers;
clearing PGLOCK allows writes.
To set or clear the PGLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” in the “PIC32 Family Reference
Manual” for details.
Name ID QOS
CPU 1 LRS
(1)
CPU 2 HIGH
(1,2)
DMA Read 3 LRS
(1)
DMA Read 4 HIGH
(1,2)
DMA Write 5 LRS
(1)
DMA Write 6 HIGH
(1,2)
USB 7 LRS
Ethernet Read 8 LRS
Ethernet Write 9 LRS
CAN1 10 LRS
CAN2 11 LRS
SQI1 12 LRS
Flash Controller 13 HIGH
(2)
Crypto 14 LRS
Note 1: When accessing SRAM, the DMAPRI bit
(CFGCON<25>) and the CPUPRI bit
(CFGCON<24>) provide arbitration con-
trol for the DMA and CPU (when servicing
an interrupt (i.e., EXL = 1)), respectively,
by selecting the use of LRS or HIGH
When using HIGH, the DMA and CPU get
arbitration preference over all initiators
using LRS.
2: Using HIGH arbitration can have serious
negative effects on other initiators.
Therefore, it is recommended to not
enable this type of arbitration for an initia
-
tor that uses significant system band-
width. HIGH arbitration is intended to be
used for low bandwidth applications that
require low latency, such as LCC graphics
applications.