Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 713
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
ADCCMPENx (ADC Digital Comparator ‘x’ Enable Reg-
ister (‘x’ = 1 through 6)).....................................462
ADCCMPx (ADC Digital Comparator ‘x’ Limit Value Reg-
ister (‘x’ = 1 through 6)).....................................463
ADCCMPxCON (ADC Digital Comparator ‘x’ Control
Register (‘x’ = 1 through 6)) .............................. 471
ADCCON1 (ADC Control Register 1) .......................439
ADCCON2 (ADC Control Register 2) .......................442
ADCCON3 (ADC Control Register 3) .......................444
ADCCSS1 (ADC Common Scan Select Register 1). 459
ADCCSS2 (ADC Common Scan Select Register 2). 460
ADCDATAx (ADC Output Data Register (‘x’ = 0 through
44)) ................................................................... 476
ADCDSTAT1 (ADC Data Ready Status Register 1). 461
ADCDSTAT2 (ADC Data Ready Status Register 2). 461
ADCEIEN1 (ADC Early Interrupt Enable Register 1) 479
ADCEIEN2 (ADC Early Interrupt Enable Register 2) 479
ADCEISTAT2 (ADC Early Interrupt Status Register 2)...
481
ADCFLTRx (ADC Digital Filter ‘x’ Register (‘x’ = 1
through 6)) ........................................................ 464
ADCGIRQEN1 (ADC Interrupt Enable Register 1) ... 458
ADCIMCON1 (ADC Input Mode Control Register 1) 449
ADCIMCON2 (ADC Input Mode Control Register 2) 452
ADCIMCON3 (ADC Input Mode Control Register 3) 455
ADCIRQEN2 (ADC Interrupt Enable Register 2)...... 458
ADCSYSCFG1 (ADC System Configuration Register 1)
485
ADCSYSCFG2 (ADC System Configuration Register 2)
485
ADCTRG1 (ADC Trigger Source 1 Register)............466
ADCTRG2 (ADC Trigger Source 2 Register)............467
ADCTRG3 (ADC Trigger Source 3 Register)............468
ADCTRGMODE (ADC Triggering Mode for Dedicated
ADC)................................................................. 447
ADCTRGSNS (ADC Trigger Level/Edge Sensitivity) 477
ADCxCFG (ADCx Configuration Register ‘x’ (‘x’ = 1
through 6)) ........................................................ 484
ADCxTIME (Dedicated ADCx Timing Register ‘x’ (‘x’ = 0
through 4)) ........................................................ 478
ALRMTIME (Alarm Time Value) ............................... 401
BFxSEQ0/ABFxSEQ0 (Boot Flash ‘x’ Sequence Word 0
Register ..............................................................70
CEBDADDR (Crypto Engine Buffer Descriptor)........ 407
CEBDPADDR (Crypto Engine Buffer Descriptor Proces-
sor).................................................................... 407
CECON (Crypto Engine Control) .............................. 406
CEHDLEN (Crypto Engine Header Length).............. 413
CEINTEN (Crypto Engine Interrupt Enable) .............411
CEINTSRC (Crypto Engine Interrupt Source)........... 410
CEPOLLCON (Crypto Engine Poll Control)..............412
CESTAT (Crypto Engine Status) .............................. 408
CETRLLEN (Crypto Engine Trailer Length).............. 413
CEVER (Crypto Engine Revision, Version, and ID).. 405
CFGEBIA (External Bus Interface Address Pin Configu-
ration)................................................................ 598
CFGEBIC (External Bus Interface Control Pin Configura-
tion)...................................................................599
CFGPG (Permission Group Configuration)...............601
CiCFG (CAN Baud Rate Configuration).................... 494
CiCON (CAN Module Control) ..................................492
CiFIFOBA (CAN Message Buffer Base Address) ..... 519
CiFIFOCIn (CAN Module Message Index Register ‘n’ (‘n’
= 0-31))............................................................. 524
CiFIFOCONn (CAN FIFO Control Register ‘n’ (‘n’ = 0-
31))................................................................... 520
CiFIFOINTn (CAN FIFO Interrupt Register ‘n’ (‘n’ = 0-
31))................................................................... 522
CiFIFOUAn (CAN FIFO User Address Register ‘n’ (‘n’ =
0-31))................................................................ 524
CiFLTCON0 (CAN Filter Control Register 0)............ 502
CiFLTCON1 (CAN Filter Control Register 1)............ 504
CiFLTCON2 (CAN Filter Control Register 2)............ 506
CiFLTCON3 (CAN Filter Control Register 3)............ 508
CiFLTCON4 (CAN Filter Control Register 4)............ 510
CiFLTCON5 (CAN Filter Control Register 5)............ 512
CiFLTCON6 (CAN Filter Control Register 6)............ 514
CiFLTCON7 (CAN Filter Control Register 7)............ 516
CiFSTAT (CAN FIFO Status) ................................... 499
CiRXFn (CAN Acceptance Filter ‘n’ Register 7 (‘n’ = 0-
31))................................................................... 518
CiRXMn (CAN Acceptance Filter Mask ‘n’ Register (‘n’ =
0-3)).................................................................. 501
CiRXOVF (CAN Receive FIFO Overflow Status) ..... 500
CiTMR (CAN Timer) ................................................. 500
CiTREC (CAN Transmit/Receive Error Count)......... 499
CiVEC (CAN Interrupt Code).................................... 498
CMSTAT (Comparator Control Register) ................. 572
CMxCON (Comparator Control) ............................... 571
CNCONx (Change Notice Control for PORTx)......... 284
CONFIG (Configuration Register - CP0 Register 16, Se-
lect 0).................................................................. 51
CONFIG1 (Configuration Register 1 - CP0 Register 16,
Select 1) ............................................................. 52
CONFIG3 (Configuration Register 3 - CP0 Register 16,
Select 3) ............................................................. 53
CONFIG5 (Configuration Register 5 - CP0 Register 16,
Select 5) ............................................................. 54
CONFIG7 (Configuration Register 7 - CP0 Register 16,
Select 7) ............................................................. 54
CVRCON (Comparator Voltage Reference Control) 575
DCHxCON (DMA Channel x Control)....................... 188
DCHxCPTR (DMA Channel x Cell Pointer).............. 196
DCHxCSIZ (DMA Channel x Cell-Size).................... 196
DCHxDAT (DMA Channel x Pattern Data) ............... 197
DCHxDPTR (Channel x Destination Pointer) ........... 195
DCHxDSA (DMA Channel x Destination
Start Address)................................................... 193
DCHxDSIZ (DMA Channel x Destination Size) ........ 194
DCHxECON (DMA Channel x Event Control) .......... 190
DCHxINT (DMA Channel x Interrupt Control)........... 191
DCHxSPTR (DMA Channel x Source Pointer) ......... 195
DCHxSSA (DMA Channel x Source Start Address) . 193
DCHxSSIZ (DMA Channel x Source Size)............... 194
DCRCCON (DMA CRC Control) .............................. 185
DCRCDATA (DMA CRC Data)................................. 187
DCRCXOR (DMA CRCXOR Enable) ....................... 187
DEVCFG0/ADEVCFG0 (Device Configuration Word 0).
588
DEVCFG1/ADEVCFG1 (Device Configuration Word 1).
590
DEVCFG2/ADEVCFG2 (Device Configuration Word 2).
593
DEVCFG3/ADEVCFG3 (Device Configuration Word 3).
595
DEVCP0/ADEVCP0 (Device Code-Protect 0).......... 587
DEVID (Device and Revision ID).............................. 602
DEVSIGN0/ADEVSIGN0 (Device Signature Word 0) ....
587
DMAADDR (DMA Address)...................................... 184