Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 704 Preliminary  2015 Microchip Technology Inc.
B.3 CPU
The CPU in PIC32MZ EC devices is the microAptiv™
MPU architecture. The CPU in the PIC32MZ EF
devices is the Series 5 Warrior M-Class M5150 MPU
architecture. Most PIC32MZ EF M-Class core features
are identical to the microAptiv™ core in PIC32MZ EC
devices. The main differences are that in PIC32MZ EF
devices, a floating-point unit (FPU) is included for
improved math performance, and PC Sampling for
performance measurement.
B.4 System Bus
The system bus on PIC32MZ EF devices is similar to
the system bus on PIC32MZ EC devices. There are
two key differences listed in
Table B-3.
B.5 Flash Controller
The Flash controller on PIC32MZ EF devices adds the
ability both to control boot Flash aliasing, and for lock
-
ing the current swap settings. Table B-4 lists theses
differences.
TABLE B-3: SYSTEM BUS DIFFERENCES
PIC32MZ EC Feature PIC32MZ EF Feature
Permission Groups during NMI
On PIC32MZ EC devices, the permission group in which the
CPU is part of is lost during NMI handling, and must be manually
restored.
On PIC32MZ EF devices, the prior permission group is
preserved, and is restored when the CPU returns from the NMI
handler.
DMA Access
The DMA can access the peripheral registers on Peripheral
Bus 1.
On PIC32MZ EF devices, the DMA no longer has access to
registers on Peripheral Bus 1. Refer to Table 4-4 for details on
which peripherals are now excluded.
TABLE B-4: FLASH CONTROLLER DIFFERENCES
PIC32MZ EC Feature PIC32MZ EF Feature
Boot Flash Aliasing
On PIC32MZ EC devices, boot flash aliasing is done through the
DEVSEQ0 register, but no further changes are possible without
rebooting the processor.
On PIC32MZ EF devices, the initial boot flash aliasing is still
determined by the DEVSEQ0 register, but the BFSWAP bit
(NVMCON<6>) reflects the state of the aliasing, and can be
modified to change it during run-time.
BFSWAP (NVMCON<6>)
1 = Boot Flash Bank 2 is mapped to the lower boot alias, and Boot
Flash bank 1 is mapped to the upper boot alias
0 = Boot Flash Bank 1 is mapped to the lower boot alias, and Boot
Flash Bank 2 is mapped to the upper boot alias
PFM and BFM Swap Locking
On PIC32MZ EC devices, the swapping of PFM is always
available.
On PIC32MZ EF devices, a new control, SWAPLOCK<1:0>
(NVMCON2<7:6>) allows the locking of PFSWAP and BFSWAP
bits, and can restrict any further changes.
SWAPLOCK<1:0> (NVMCON2<7:6>)
11 = PFSWAP and BFSWAP are not writable and SWAPLOCK is
not writable
10 = PFSWAP and BFSWAP are not writable and SWAPLOCK is
writable
01 = PFSWAP and BFSWAP are not writable and SWAPLOCK is
writable
00 = PFSWAP and BFSWAP are writable and SWAPLOCK is
writable