Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 702 Preliminary  2015 Microchip Technology Inc.
APPENDIX B: MIGRATING FROM
PIC32MZ EC TO
PIC32MZ EF
This appendix provides an overview of considerations
for migrating from PIC32MZ EC devices to the
PIC32MZ EF family of devices. The code developed for
PIC32MZ EC devices can be ported to PIC32MZ EF
devices after making the appropriate changes outlined
in the following sections.
The PIC32MZ EF devices are similar to PIC32MZ EC
devices, with many feature improvements and new
capabilities.
B.1 Oscillator and PLL Configuration
A number of new features have been added to the
oscillator and PLL to enhance their ability to work with
crystals and to change frequencies.
Table B-1 summarizes the differences (indicated by
Bold type) between the family differences for the
oscillator.
TABLE B-1: OSCILLATOR DIFFERENCES
PIC32MZ EC Feature PIC32MZ EF Feature
Primary Oscillator Crystal Power
On PIC32MZ EC devices, the crystal HS P
OSC mode is only
functional with crystals that have certain characteristics, such as
very low ESR.
On PIC32MZ EF devices, some DEVCFG0 bits have been
added to allow control over the strength of the oscillator and to
add a kick start boost.
POSCBOOST (DEVCFG0<21>)
1 = Boost the kick start of the oscillator
0 = Normal start of the oscillator
POSCGAIN<1:0> (DEVCFG0<20:19>)
11 = 2x gain setting
10 = 1.5x gain setting
01 = 0.5x gain setting
00 = 1x gain setting
Note that the default for POSCGAIN (2x gain setting) may over-
drive crystals and shorten their life. It is the responsibility of the
designer to ensure crystals are operated properly.
Secondary Oscillator Crystal Power
On PIC32MZ EC devices, the Secondary Oscillator (S
OSC) is not
functional.
On PIC32MZ EF devices, the Secondary Oscillator is now
functional, and provides similar strength and kick start boost
features as the P
OSC.
SOSCBOOST (DEVCFG0<18>)
1 = Boost the kick start of the oscillator
0 = Normal start of the oscillator
SOSCGAIN<1:0> (DEVCFG0<17:16>)
11 = 2x gain setting
10 = 1.5x gain setting
01 = 0.5x gain setting
00 = 1x gain setting
Note that the default for SOSCGAIN (2x gain setting) may over-
drive crystals and shorten their life. It is the responsibility of the
designer to ensure crystals are operated properly.
Clock Status Bits
On PIC32MZ EC devices, the SOSCRDY bit (OSCCON<22>)
indicates when the Secondary Oscillator is ready. There are no
indications of other oscillator status.
A new register, CLKSTAT, has been added, which includes the
SOSCRDY bit (CLKSTAT<4>). In addition, new status bits are
available:
• LPRCRDY (CLKSTAT<5>)
• POSCRDY (CLKSTAT<2>)
• DIVSPLLRDY (CLKSTAT<1>)
• FRCRDY (CLKSTAT<0>)
Clock Switching
On PIC32MZ EC devices, clock switches occur as soon as the
switch command is issued. Also, the only clock sources that can
be divided are the output of the PLL, and the FRC.
To reduce power spikes during clock switches, PIC32MZ EF
devices add a clock slewing feature, so that clock switches can
be controlled in their rate and size. The SLEWCON register
controls this feature. The SLEWCON register also features a
SYSCLK divider, so that all of the possible clock sources may be
divided further as needed.