Datasheet
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 700 Preliminary 2015 Microchip Technology Inc.
Ethernet
On PIC32MZ EF devices, the input clock divider for the Ethernet
module has expanded options to accommodate the faster
peripheral bus clock.
CLKSEL<3:0> (EMAC1MCFG<5:2>)
1000 = SYSCLK divided by 40
0111 = SYSCLK divided by 28
0110 = SYSCLK divided by 20
0101 = SYSCLK divided by 14
0100 = SYSCLK divided by 10
0011 = SYSCLK divided by 8
0010 = SYSCLK divided by 6
000x = SYSCLK divided by 4
CLKSEL<3:0> (EMAC1MCFG<5:2>)
1010 = PBCLK5 divided by 50
1001 = PBCLK5 divided by 48
1000 = PBCLK5 divided by 40
0111 = PBCLK5 divided by 28
0110 = PBCLK5 divided by 20
0101 = PBCLK5 divided by 14
0100 = PBCLK5 divided by 10
0011 = PBCLK5 divided by 8
0010 = PBCLK5 divided by 6
000x = PBCLK5 divided by 4
Comparator/Comparator Voltage Reference
On PIC32MX devices, it was possible to select the V
REF+ pin as
the output to the CV
REFOUT pin.
On PIC32MZ EF devices, the CV
REFOUT pin must come from the
resistor network.
VREFSEL (CVRCON<10>)
1 = CV
REF = VREF+
0 = CV
REF is generated by the resistor network
This bit is not available.
On PIC32MX devices, the internal voltage reference (IV
REF)
could be chosen by the BGSEL<1:0> bits.
On PIC32MZ EF devices, IVREF is fixed and cannot be changed.
BGSEL<1:0> (CVRCON<9:8>)
11 = IV
REF = VREF+
10 = Reserved
01 = IV
REF = 0.6V (nominal, default)
00 = IV
REF = 1.2V (nominal)
These bits are not available.
Change Notification
On PIC32MX devices, Change Notification is controlled by the
CNCON, CNEN, and CNPUE registers.
On PIC32MZ EF devices, Change Notification functionality has
been relocated into each I/O port and is controlled by the
CNPUx, CNPDx, CNCONx, CNENx, and CNSTATx registers.
System Bus
On PIC32MX devices, the System Bus registers can be used to
configure RAM memory for data and program memory partitions,
cacheability of Flash memory, and RAM Wait states. These reg-
isters are: BMXCON, BMXDKPBA, BMXDUDBA, BMXDUPBA,
BMXPUPBA, BMXDRMSZ, BMXPFMSZ, and BMXBOOTSZ.
On PIC32MZ EF devices, a new System Bus is utilized that sup-
ports using RAM memory for program or data without the need
for special configuration. Therefore, no special registers are
associated with the System Bus to configure these features.
On PIC32MX devices, various arbitration modes are used as ini-
tiators on the System Bus. These modes can be selected by the
BMXARB<2:0> (BMXCON<2:0>) bits.
On PIC32MZ EF devices, a new arbitration scheme has been
implemented on the System Bus. All initiators use the Least
Recently Serviced (LRS) scheme, with the exception of the
DMA, CPU, and the Flash Controller.
The Flash Controller always has High priority over LRS initiators.
The DMA and CPU (when servicing an interrupt) can be selected
to have LRS or High priority using the DMAPRI (CFGCON<25>)
and CPUPRI (CFGCON<24>) bits.
TABLE A-10: PERIPHERAL DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature