Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 698 Preliminary  2015 Microchip Technology Inc.
Flash Programming
The op codes for programming the Flash memory have been
changed to accommodate the new quad-word programming and
dual-panel features. The row size has changed to 2 KB (512 IW)
from 128 IW. The page size has changed to 16 KB (4K IW) from
4 KB (1K IW). Note that the NVMOP register is now protected,
and requires the WREN bit be set to enable modification.
NVMOP<3:0> (NVMCON<3:0>)
1111 = Reserved
•
•
•
0111 = Reserved
0110 = No operation
0101 = Program Flash (PFM) erase operation
0100 = Page erase operation
0011 = Row program operation
0010 = No operation
0001 = Word program operation
0000 = No operation
NVMOP<3:0> (NVMCON<3:0>)
1111 = Reserved
•
•
•
1000 = Reserved
0111 = Program erase operation
0110 = Upper program Flash memory erase operation
0101 = Lower program Flash memory erase operation
0100 = Page erase operation
0011 = Row program operation
0010 = Quad Word (128-bit) program operation
0001 = Word program operation
0000 = No operation
PIC32MX devices feature a single NVMDATA register for word
programming.
On PIC32MZ EF devices, to support quad word programming,
the NVMDATA register has been expanded to four words.
NVMDATA NVMDATAx, where ‘x’ = 0 through 3
Flash Endurance and Retention
PIC32MX devices support Flash endurance and retention of up
to 20K E/W cycles and 20 years.
On PIC32MZ EF devices, ECC must be enabled to support the
same endurance and retention as PIC32MX devices.
Configuration Words
On PIC32MX devices, Configuration Words can be programmed
with Word or Row program operation.
On PIC32MZ EF devices, all Configuration Words must be
programmed with Quad Word operation.
Configuration Words Reserved Bit
On PIC32MX devices, the DEVCFG0<15> bit is Reserved and
must be programmed to ‘
0’.
On PIC32MZ EF devices, this bit is DEVSIGN0<31>.
TABLE A-9: FLASH PROGRAMMING DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature