Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 696 Preliminary  2015 Microchip Technology Inc.
A.7 Interrupts and Exceptions
The key difference between Interrupt Controllers in
PIC32MX5XX/6XX/7XX devices and PIC32MZ EF
devices concerns vector spacing. Previous PIC32MX
devices had fixed vector spacing, which is adjustable in
set increments, and every interrupt had the same
amount of space. PIC32MZ EF devices replace this
with a variable offset spacing, where each interrupt has
an offset register to determine where to begin
execution.
In addition, the IFSx, IECx, and IPCx registers for old
peripherals have shifted to different registers due to
new peripherals. Please refer to Section 7.0 “CPU
Exceptions and Interrupt Controller” to determine
where the interrupts are now located.
Table A-8 lists differences (indicated by Bold type) in
the registers that will affect software migration.
TABLE A-8: INTERRUPT DIFFERENCES
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature
Vector Spacing
On PIC32MX devices, the vector spacing was determined by the
VS field in the CPU core.
On PIC32MZ EF devices, the vector spacing is variable and
determined by the Interrupt controller. The VOFFx<17:1> bits in
the OFFx register are set to the offset from EBASE where the
interrupt service routine is located.
VS<4:0> (IntCtl<9:5>: CP0 Register 12, Select 1)
10000 = 512-byte vector spacing
01000 = 256-byte vector spacing
00100 = 128-byte vector spacing
00010 = 64-byte vector spacing
00001 = 32-byte vector spacing
00000 = 0-byte vector spacing
VOFFx<17:1> (OFFx<17:1>)
Interrupt Vector ‘x’ Address Offset bits
Shadow Register Sets
On PIC32MX devices, there was one shadow register set which
could be used during interrupt processing. Which interrupt priority
could use the shadow register set was determined by the FSRS-
SEL field in DEVCFG3 and SS0 on INTCON.
On PIC32MZ EF devices, there are seven shadow register sets,
and each priority level can be assigned a shadow register set to
use via the PRIxSS<3:0> bits in the PRISS register. The SS0 bit
is also moved to PRISS<0>.
FSRSSEL<2:0> (DEVCFG3<18:16>)
111 = Assign Interrupt Priority 7 to a shadow register set
110 = Assign Interrupt Priority 6 to a shadow register set
•
•
•
001 = Assign Interrupt Priority 1 to a shadow register set
000 = All interrupt priorities are assigned to a shadow 
register set
PRIxSS<3:0> PRISS<y:z>
1xxx = Reserved (by default, an interrupt with a priority
level of x uses Shadow Set 0)
0111 = Interrupt with a priority level of x uses Shadow Set 7
0110 = Interrupt with a priority level of x uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of x uses Shadow Set 1
0000 = Interrupt with a priority level of x uses Shadow Set 0
SS0 (INTCON<16>)
1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set
SS0 (PRISS<0>)
1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set
Status
PIC32MX devices, the VEC<5:0> bits show which interrupt is
being serviced.
On PIC32MZ EF devices, the SIRQ<7:0> bits show the IRQ
number of the interrupt last serviced.
VEC<5:0> (INTSTAT<5:0>)
11111-00000 = The interrupt vector that is presented to the
CPU
SIRQ<7:0> (INTSTAT<7:0>)
11111111-00000000 = The last interrupt request number
serviced by the CPU