Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 695
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.6 DMA
The DMA controller in PIC32MZ EF devices is similar
to the DMA controller in PIC32MX5XX/6XX/7XX
devices. New features include the extension of pattern
matching to two by bytes and the addition of the
optional Pattern Ignore mode. Table A-7 lists differ-
ences (indicated by Bold type) that will affect software
migration.
TABLE A-7: DMA DIFFERENCES
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature
Read/Write Status on Error
The RDWR bit has moved from DMASTAT<3> in PIC32MX5XX/
6XX/7XX devices to DMASTAT<31> in PIC32MZ EF devices.
RDWR (DMASTAT<3>)
1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write
RDWR (DMASTAT<31>)
1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write
Source-to-Destination Transfer
On PIC32MX devices, a DMA channel performs a read of the
source data and completes the transfer of this data into the desti
-
nation address before it is ready to read the next data from the
source.
On PIC32MZ EF devices, the DMA implements a 4-deep queue
for data transfers. A DMA channel reads the source data and
places it into the queue, regardless of whether previous data in
the queue has been delivered to the destination address.