Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 693
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.3 CPU
The CPU in the PIC32MZ EF family of devices has
been changed to the MIPS32 M-Class MPU architec
-
ture. This CPU includes DSP ASE, internal data and
instruction L1 caches, and a TLB-based MMU.
Table A-4 summarizes some of the key differences
(indicated by Bold type) in the internal CPU registers.
TABLE A-4: CPU DIFFERENCES
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature
L1 Data and Instruction Cache and Prefetch Wait States
On PIC32MX devices, the cache was included in the prefetch
module outside the CPU.
On PIC32MZ EF devices, the CPU has a separate L1 instruction
and data cache in the core. The PREFEN<1:0> bits still enable
the prefetch module; however, the K0<2:0> bits in the CP0 regis-
ters controls the internal L1 cache for the designated regions.
PREFEN<1:0> (CHECON<5:4>)
11 = Enable predictive prefetch for both cacheable and 
non-cacheable regions
10 = Enable predictive prefetch for non-cacheable regions only
01 = Enable predictive prefetch for cacheable regions only
00 = Disable predictive prefetch
DCSZ<1:0> (CHECON<9:8>)
Changing these bits causes all lines to be reinitialized to the
“invalid” state.
11 = Enable data caching with a size of 4 lines
10 = Enable data caching with a size of 2 lines
01 = Enable data caching with a size of 1 line
00 = Disable data caching
CHECOH (CHECON<16>)
1 = Invalidate all data and instruction lines
0 = Invalidate all data and instruction lines that are not locked
PREFEN<1:0> (PRECON<5:4>)
11 = Enable predictive prefetch for any address
10 = Enable predictive prefetch for CPU instructions and CPU
data
01 = Enable predictive prefetch for CPU instructions only
00 = Disable predictive prefetch
K0<2:0> (CP0 Reg 16, Select 0)
011 = Cacheable, non-coherent, write-back, write allocate
010 = Uncached
001 = Cacheable, non-coherent, write-through, write allocate
000 = Cacheable, non-coherent, write-through, no write allocate
The Program Flash Memory read wait state frequency points
have changed in PIC32MZ EF devices. The register for accessing
the PFMWS field has changed from CHECON to PRECON.
PFMWS<2:0> (CHECON<2:0>)
111 = Seven Wait states
110 = Six Wait states
101 = Five Wait states
100 = Four Wait states
011 = Three Wait states
010 = Two Wait states (61-80 MHz)
001 = One Wait state (31-60 MHz)
000 = Zero Wait state (0-30 MHz)
PFMWS<2:0> (PRECON<2:0>)
111 = Seven Wait states
•
•
•
011 = Three Wait states
010 = Two Wait states (133-200 MHz)
001 = One Wait state (66-133 MHz)
000 = Zero Wait states (0-66 MHz)
Note: Wait states listed are for ECC enabled.
Core Instruction Execution
On PIC32MX devices, the CPU can execute MIPS16e
instructions and uses a 16-bit instruction set, which reduces
memory size.
On PIC32MZ EF devices, the CPU can operate a mode called
microMIPS. microMIPS mode is an enhanced MIPS32®
instruction set that uses both 16-bit and 32-bit opcodes. This
mode of operation reduces memory size with minimum
performance impact.
MIPS16e
®
microMIPS™
The BOOTISA (DEVCFG0<6>) Configuration bit controls the
MIPS32 and microMIPS modes for boot and exception code.
1 = Boot code and Exception code is MIPS32
®
(ISAONEXC bit is
set to ‘0’ and the ISA<1:0> bits are set to ‘10’ in the CP0 Config3
register)
0 = Boot code and Exception code is microMIPS™ (ISAONEXC
bit is set to ‘1’ and the ISA<1:0> bits are set to ‘11’ in the CP0
Config3 register)