Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 691
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.2 Analog-to-Digital Converter (ADC)
The PIC32MZ EF family of devices has a new Pipe-
lined ADC module that replaces the 10-bit ADC module
in PIC32MX5XX/6XX/7XX devices; therefore, the use
of Bold type to show differences is not used in the fol-
lowing table. Note that not all register differences are
described in this section; however, the key feature
differences are listed in Table A-3.
TABLE A-3: ADC DIFFERENCES
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature
Clock Selection and Operating Frequency (T
AD)
On PIC32MX devices, the ADC clock was derived from either the
FRC or from the PBCLK.
On PIC32MZ EF devices, the three possible sources of the ADC
clock are FRC, REFCLKO3, and SYSCLK.
ADRC (AD1CON3<15>)
1 = FRC clock
0 = Clock derived from Peripheral Bus Clock (PBCLK)
ADCSEL<1:0> (ADCCON3<31:30>)
11 = FRC
10 = REFCLKO3
01 = SYSCLK
00 = Reserved
On PIC32MX devices, if the ADC clock was derived from the
PBCLK, that frequency was divided further down, with a maxi-
mum divisor of 512, and a minimum divisor of two.
On PIC32MZ EF devices, any ADC clock source can be divided
down separately for each dedicated ADC and the shared ADC,
with a maximum divisor of 254. The input clock can also be fed
directly to the ADC.
ADCS<7:0> (AD1CON3<7:0>)
11111111 = 512 * T
PB = TAD
•
•
•
00000001 = 4 * TPB = TAD
00000000 = 2 * TPB = TAD
ADCDIV<6:0> (ADCTIMEx<22:16>)
ADCDIV<6:0> (ADCCON2<6:0>)
1111111 = 254 * T
Q = TAD
•
•
•
0000011 = 6 * TQ = TAD
0000010 = 4 * TQ = TAD
0000001 = 2 * TQ = TAD
0000000 = TQ = TAD
Scan Trigger Source
On PIC32MX devices, there are four sources that can trigger a
scan conversion in the ADC module: Auto, Timer3, INT0, and
clearing the SAMP bit.
On PIC32MZ EF devices, the list of sources for triggering a scan
conversion has been expanded to include the comparators,
Output Compare, and two additional Timers. In addition, trigger
sources can be simulated by setting the RQCNVRT
(ADCCON3<8>) bit.
SSRC<2:0> (AD1CON1<7:5>)
111 = Auto convert
110 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = Timer3 period match
001 = Active transition on INT0 pin
000 = Clearing SAMP bit
STRGSRC<4:0> (ADCCON1<20:16>)
11111 = Reserved
•
•
•
01101 = Reserved
01100 = Comparator 2 COUT
01011 = Comparator 1 COUT
01010 = OCMP5
01001 = OCMP3
01000 = OCMP1
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0
00011 = Reserved
00010 = Global level software trigger (GLSWTRG)
00001 = Global software trigger (GSWTRG)
00000 = No trigger