Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 690 Preliminary  2015 Microchip Technology Inc.
Table A-2 illustrates the difference in code setup of the
respective parts for maximum speed using an external
24 MHz crystal.
TABLE A-2: CODE DIFFERENCES FOR MAXIMUM SPEED USING AN EXTERNAL 24 MHz
CRYSTAL
Fail-Safe Clock Monitor (FSCM)
On PIC32MX devices, the internal FRC became the clock source
on a failure of the clock source.
On PIC32MZ EF devices, a separate internal Backup FRC
(BFRC) becomes the clock source upon a failure at the clock
source.
On PIC32MX devices, a clock failure resulted in the triggering of
a specific interrupt when the switchover was complete.
On PIC32MZ EF devices, a NMI is triggered instead, and must be
handled by the NMI routine.
FSCM generates an interrupt. FSCM generates a NMI.
The definitions of the FCKSM<1:0> bits has changed on
PIC32MZ EF devices.
FCKSM<1:0> (DEVCFG1<15:14>)
1x = Clock switching is disabled, FSCM is disabled
01 = Clock switching is enabled, FSCM is disabled
00 = Clock switching is enabled, FSCM is enabled
FCKSM<1:0> (DEVCFG1<15:14>)
11 = Clock switching is enabled and clock monitoring 
is enabled
10 = Clock switching is disabled and clock monitoring 
is enabled
01 = Clock switching is enabled and clock monitoring is disabled
00 = Clock switching is disabled and clock monitoring 
is disabled
On PIC32MX devices, the CF (OSCCON<3>) bit indicates a
clock failure. Writing to this bit initiates a FSCM event.
On PIC32MZ EF devices, the CF (OSCCON<3>) bit has the
same functionality as that of PIC32MX device; however, an addi
-
tional CF(RNMICON<1>) bit is available to indicate a NMI event.
Writing to this bit causes a NMI event, but not a FSCM event.
On PIC32MX devices, the CLKLOCK (OSCCON<7>) bit is
controlled by the FSCM.
On PIC32MZ EF devices, the CLKLOCK (OSCCON<7>) bit is
not impacted by the FSCM.
CLKLOCK (OSCCON<7>)
If clock switching and monitoring is disabled (FCKSM<1:0> = 1x):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
If clock switching and monitoring is enabled (FCKSM<1:0> = 0x):
Clock and PLL selections are never locked and may be modified.
CLKLOCK (OSCCON<7>)
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
TABLE A-1: OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature
PIC32MX5XX/6XX/7XX @ 80 Hz PIC32MZ EF @ 200 MHz
#include <xc.h>
#pragma config POSCMOD = HS
#pragma config FNOSC = PRIPLL
#pragma config FPLLIDIV = DIV_6
#pragma config FPLLMUL = MUL_20
#pragma config FPLLODIV = DIV_1
#define SYSFREQ (80000000L)
#include <xc.h>
#pragma config POSCMOD = HS
#pragma config FNOSC = SPLL
#pragma config FPLLICLK = PLL_POSC
#pragma config FPLLIDIV = DIV_3
#pragma config FPLLRNG = RANGE_5_10_MHZ
#pragma config FPLLMULT = MUL_50
#pragma config FPLLODIV = DIV_2
#define SYSFREQ (200000000L)