Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 689
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Crystal/Oscillator Selection for USB
Any frequency that can be divided down to 4 MHz using
UPLLIDIV, including 4, 8, 12, 16, 20, 40, and 48
MHz.
If the USB module is used, the Primary Oscillator is limited to
either 12
MHz or 24 MHz. Which frequency is used is selected
using the UPLLFSEL (DEVCFG2<30>) bit.
USB PLL Configuration
On PIC32MX devices, the PLL for the USB requires an input fre-
quency of 4 MHz.
On PIC32MZ EF devices, the HS USB PHY requires an input
frequency of 12 MHz or 24
MHz. UPLLIDIV has been replaced
with UPLLFSEL.
UPLLIDIV<2:0> (DEVCFG2<10:8>)
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
UPLLFSEL (DEVCFG2<30>)
1 = UPLL input clock is 24 MHz
0 = UPLL input clock is 12 MHz
Peripheral Bus Clock Configuration
On PIC32MX devices, there is one peripheral bus, and the clock
for that bus is divided from the SYSCLK using FPBDIV/PBDIV. In
addition, the maximum PBCLK frequency is the same as
SYSCLK.
On PIC32MZ EF devices, there are eight peripheral buses with
their own clocks. FPBDIV is removed, and each PBDIV is in its
own register for each PBCLK. The initial PBCLK speed is fixed at
reset, and the maximum PBCLK speed is limited to100 MHz for
all buses, with the exception of PBCLK7, which is 200 MHz.
FPBDIV<1:0> (DEVCFG1<5:4>)
PBDIV<1:0> (OSCCON<20:19>)
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
PBDIV<6:0> (PBxDIV<6:0>)
1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127
•
•
•
0000011 = PBCLKx is SYSCLK divided by 4
0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2
(default value for x < 7)
0000000 = PBCLKx is SYSCLK divided by 1
(default value for x 7)
CPU Clock Configuration
On PIC32MX devices, the CPU clock is derived from SYSCLK. On PIC32MZ EF devices, the CPU clock is derived from PBCLK7.
FRCDIV Default
On PIC32MX devices, the default value for FRCDIV was to divide
the FRC clock by two.
On PIC32MZ EF devices, the default has been changed to divide
by one.
FRCDIV<2:0> (OSCCON<26:24>)
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2 (default)
000 = FRC divided by 1
FRCDIV<2:0> (OSCCON<26:24>)
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default)
TABLE A-1: OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature