Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 688 Preliminary  2015 Microchip Technology Inc.
PLL Configuration
The FNOSC<2:0> and NOSC<2:0> bits select between POSC
and FRC.
Selection of which input clock (POSC or FRC) is now done
through the FPLLICLK/PLLICLK bits.
FNOSC<2:0> (DEVCFG1<2:0>)
NOSC<2:0> (OSCCON<10:8>)
FPLLICLK (DEVCFG2<7>)
PLLICLK (SPLLCON<7>)
On PIC32MX devices, the input frequency to the PLL had to be
between 4 MHz and 5 MHz. FPLLIDIV selected how to divide the
input frequency to give it the appropriate range.
On PIC32MZ EF devices, the input range for the PLL is wider (5
MHz to 64 MHz). The input divider values have changed, and new
FPLLRNG/PLLRNG bits have been added to indicate under what
range the input frequency falls.
FPLLIDIV<2:0> (DEVCFG2<2:0>)
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
FPLLIDIV<2:0> (DEVCFG2<2:0>)
PLLIDIV<2:0> (SPLLCON<2:0>)
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
FPLLRNG<2:0> (DEVCFG2<6:4>)
PLLRNG<2:0> (SPLLCON<2:0>)
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
On PIC32MX devices, the output frequency of PLL is between
60 MHz and 120 MHz. The PLL multiplier and divider bits
configure the PLL for this range.
The PLL multiplier and divider on PIC32MZ EF devices have a
wider range to accommodate the wider PLL specification range of
10 MHz to 200 MHz.
FPLLMUL<2:0> (DEVCFG2<6:4>)
PLLMULT<2:0> (OSCCON<18:16>)
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
FPLLMULT<6:0> (DEVCFG2<14:8>)
PLLMULT<6:0> (SPLLCON<22:16>)
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
FPLLODIV<2:0> (DEVCFG2<18:16>)
PLLODIV<2:0> (OSCCON<29:27>)
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
FPLLODIV<2:0> (DEVCFG2<18:16>)
PLLODIV<2:0> (SPLLCON<26:24>)
111 = PLL Divide by 32
110 = PLL Divide by 32
101 = PLL Divide by 32
100 = PLL Divide by 16
011 = PLL Divide by 8
010 = PLL Divide by 4
001 = PLL Divide by 2
000 = PLL Divide by 2
TABLE A-1: OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature