Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 687
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
APPENDIX A: MIGRATING FROM
PIC32MX5XX/6XX/7XX
TO PIC32MZ EF
This appendix provides an overview of considerations
for migrating from PIC32MX5XX/6XX/7XX devices to
the PIC32MZ EF family of devices. The code devel-
oped for PIC32MX5XX/6XX/7XX devices can be
ported to PIC32MZ EF devices after making the
appropriate changes outlined in the following sections.
The PIC32MZ EF devices are based on a new
architecture, and feature many improvements and new
capabilities over PIC32MX5XX/6XX/7XX devices.
A.1 Oscillator and PLL Configuration
Because the maximum speed of the PIC32MZ EF
family is 200 MHz, the configuration of the oscillator is
different from prior PIC32MX5XX/6XX/7XX devices.
Table A-1 summarizes the differences (indicated by
Bold type) between the family devices for the oscillator.
TABLE A-1: OSCILLATOR CONFIGURATION DIFFERENCES
PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature
Primary Oscillator Configuration
On PIC32MX devices, XT mode had to be selected if the input fre-
quency was in the 3 MHz to 10 MHz range (4-10 for PLL), and HS
mode had to be selected if the input frequency was in the 10 MHz
to 20 MHz range.
On PIC32MZ EF devices, HS mode has a wider input frequency
range (4 MHz to 12 MHz). The bit setting of ‘01’ is Reserved.
POSCMOD<1:0> (DEVCFG1<9:8>)
11 = Primary Oscillator disabled
10 = HS Oscillator mode selected
01 = XT Oscillator mode selected
00 = External Clock mode selected
POSCMOD<1:0> (DEVCFG1<9:8>)
11 = Primary Oscillator disabled
10 = HS Oscillator mode selected
01 = Reserved
00 = External Clock mode selected
Oscillator Selection
On PIC32MX devices, clock selection choices are as follows: On PIC32MZ EF devices, clock selection choices are as follows:
FNOSC<2:0> (DEVCFG1<2:0>)
NOSC<2:0> (OSCCON<10:8>)
111 = FRCDIV
110 = FRCDIV16
101 = LPRC
100 = SOSC
011 = POSC with PLL module
010 = POSC (XT, HS, EC)
001 = FRCDIV+PLL
000 = FRC
FNOSC<2:0> (DEVCFG1<2:0>)
NOSC<2:0> (OSCCON<10:8>)
111 = FRCDIV
110 = Reserved
101 = LPRC
100 = SOSC
011 = Reserved
010 = POSC (HS or EC)
001 = System PLL (SPLL)
000 = FRCDIV
COSC<2:0> (OSCCON<14:12>)
111 = FRC divided by FRCDIV
110 = FRC divided by 16
101 = LPRC
100 = SOSC
011 = POSC + PLL module
010 = POSC
001 = FRCPLL
000 = FRC
COSC<2:0> (OSCCON<14:12>)
111 = FRC divided by FRCDIV
110 = BFRC
101 = LPRC
100 = SOSC
011 = Reserved
010 = POSC
001 = System PLL
000 = FRC divided by FRCDIV
Secondary Oscillator Enable
The location of the SOSCEN bit in the Flash Configuration Words
has moved.
FSOSCEN (DEVCFG1<5>) FSOSCEN (DEVCFG1<6>)