Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 626 Preliminary  2015 Microchip Technology Inc.
TABLE 37-18: SYSTEM TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.1V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial 
-40°C  TA  +125°C for Extended
Param.
No.
Symbol Characteristics Minimum Typical Maximum Units Conditions
OS51 FSYS System Frequency DC — 200 MHz USB module disabled
30 — 200 MHz USB module enabled
OS55a FPB Peripheral Bus Frequency DC — 100 MHz For PBCLKx, ‘x’  7
OS55b DC — 200 MHz For PBCLK7
OS56 FREF Reference Clock Frequency — — 50 MHz For REFCLKI1, 3, 4
and REFCLKO1, 3, 4
pins
TABLE 37-19: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 2.1V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial 
-40°C  TA  +125°C for Extended
Param.
No.
Symbol Characteristics
(1)
Min. Typical Max. Units Conditions
OS50
FIN PLL Input Frequency Range 5 — 64 MHz ECPLL, HSPLL, FRCPLL
modes
OS52 TLOCK PLL Start-up Time (Lock Time) — — 100 µs —
OS53 DCLK CLKO Stability
(2)
(Period Jitter or Cumulative)
-0.25 — +0.25 % Measured over 100 ms
period
OS54 FVCO PLL VCO Frequency Range 350 — 700 MHz —
OS54a FPLL PLL Output Frequency Range 10 — 200 MHz —
Note 1: These parameters are characterized, but not tested in manufacturing.
2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
For example, if PBCLK2 = 100 MHz and SPI bit rate = 50 MHz, the effective jitter is as follows:
EffectiveJitter
D
CLK
PBCLK2
CommunicationClock
----------------------------------------------------------
--------------------------------------------------------------=
EffectiveJitter
D
CLK
100
50
---------
--------------
D
CLK
1.41
--------------==