Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 61

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

4.0 MEMORY ORGANIZATION

PIC32MZ EF microcontrollers provide 4 GB of unified

virtual memory address space. All memory regions, in

cluding program, data memory, SFRs and Configura-

tion registers, reside in this address space at their

respective unique addresses. The program and data

memories can be optionally partitioned into user and

kernel memories. In addition, PIC32MZ EF devices

allow execution from data memory.

Key features include:

• 32-bit native data width

• Separate User (KUSEG) and Kernel (KSEG0/

KSEG1/KSEG2/KSEG3) mode address space

• Separate boot Flash memory for protected code

• Robust bus exception handling to intercept 

runaway code

• Cacheable (KSEG0/KSEG2) and non-cacheable

(KSEG1/KSEG3) address regions

• Read-Write permission access to predefined

memory regions

4.1 Memory Layout

PIC32MZ EF microcontrollers implement two address

schemes: virtual and physical. All hardware resources,

such as program memory, data memory and peripher

als, are located at their respective physical addresses.

Virtual addresses are exclusively used by the CPU to

fetch and execute instructions as well as access pe

ripherals. Physical addresses are used by bus master

peripherals, such as DMA and the Flash controller, that

access memory independently of the CPU.

The main memory maps for the PIC32MZ EF devices

are illustrated in

Figure 4-1 through Figure 4-4.

Figure 4-5 provides memory map information for boot

Flash and boot alias. Table 4-1 provides memory map

information for Special Function Registers (SFRs).

Note: This data sheet summarizes the features

of the PIC32MZ EF family of devices. It is

not intended to be a comprehensive

reference source.For detailed information,

refer to Section 48. “Memory Organiza

tion and Permissions” in the “PIC32

Family Reference Manual”, which is avail

able from the Microchip web site

(