Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 603
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
34.3 On-Chip Voltage Regulator
The core and digital logic for all PIC32MZ EF devices
is designed to operate at a nominal 1.8V. To simplify
system designs, devices in the PIC32MZ EF family
incorporate an on-chip regulator providing the required
core logic voltage from V
DD.
34.3.1 ON-CHIP REGULATOR AND POR
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as T
PU, code
execution is disabled. T
PU is applied every time the
device resumes operation after any power-down,
including Sleep mode.
34.3.2 ON-CHIP REGULATOR AND BOR
PIC32MZ EF devices also have a simple brown-out
capability. If the voltage supplied to the regulator is
inadequate to maintain a regulated level, the regulator
Reset circuitry will generate a Brown-out Reset. This
event is captured by the BOR flag bit (RCON<1>). The
brown-out voltage levels are specific in
Section 37.1
“DC Characteristics”.
34.4 On-chip Temperature Sensor
PIC32MZ EF devices include a temperature sensor
that provides accurate measurement of a device’s
junction temperature (see Section 37.2 “AC
Characteristics and Timing Parameters” for more
information).
The temperature sensor is connected to the ADC
module and can be measured using the shared S&H
circuit (see
Section 28.0 “12-bit High-Speed
Successive Approximation Register (SAR) Analog-
to-Digital Converter (ADC)” for more information).
34.5 Programming and Diagnostics
PIC32MZ EF devices provide a complete range of pro-
gramming and diagnostic features that can increase
the flexibility of any application using them. These
features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
PIC32 devices incorporate two programming and diag-
nostic modules, and a trace controller, that provide a
range of functions to the application developer.
FIGURE 34-1: BLOCK DIAGRAM OF
PROGRAMMING,
DEBUGGING AND TRACE
PORTS
TDI
TDO
TCK
TMS
JTAG
Controller
ICSP™
Controller
Core
JTAGEN DEBUG<1:0>
ICESEL
PGEC1
PGED1
PGEC2
PGED2
Instruction Trace
Controller
DEBUG<1:0>
TRCLK
TRD0
TRD2
TRD3
TRD1