Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

DS60001320B-page 60 Preliminary  2015 Microchip Technology Inc.

bit 16 V: Invalid Operation bit

bit 15 Z: Divide-by-Zero bit

bit 14 O: Overflow bit

bit 13 U: Underflow bit

bit 12 I: Inexact bit

bit 11-7 ENABLES<4:0>: FPU Exception Enable bits

These bits control whether or not a trap is taken when an IEEE exception condition occurs for any of the

five conditions. The trap occurs when both an enable bit and its corresponding cause bit are set either

during an FPU arithmetic operation or by moving a value to the FCSR or one of its alternative

representations.

bit 11 V: Invalid Operation bit

bit 10 Z: Divide-by-Zero bit

bit 9 O: Overflow bit

bit 8 U: Underflow bit

bit 7 I: Inexact bit

bit 6-2 FLAGS<4:0>: FPU Flags bits

These bits show any exception conditions that have occurred for completed instructions since the flag was

last reset by software.

bit 6 V: Invalid Operation bit

bit 5 Z: Divide-by-Zero bit

bit 4 O: Overflow bit

bit 3 U: Underflow bit

bit 2 I: Inexact bit

bit 1-0 RM<1:0>: Rounding Mode control bits

11 = Round towards Minus Infinity (

– )

10 = Round towards Plus Infinity (

+ )

01 = Round toward Zero (0)

00 = Round to Nearest