Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 596 Preliminary  2015 Microchip Technology Inc.
REGISTER 34-7: CFGCON: CONFIGURATION CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — DMAPRI
(1)
CPUPRI
(1)
23:16
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — ICACLK
(1)
OCACLK
(1)
15:8
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0
— — IOLOCK
(1)
PMDLOCK
(1)
PGLOCK
(1)
— — USBSSEN
(1)
7:0
R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 U-0 R/W-1
IOANCPEN — ECCCON<1:0> JTAGEN TROEN —TDOEN
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25 DMAPRI: DMA Read and DMA Write Arbitration Priority to SRAM bit
(1)
1 = DMA gets High Priority access to SRAM
0 = DMA uses Least Recently Serviced Arbitration (same as other initiators)
bit 24 CPUPRI: CPU Arbitration Priority to SRAM When Servicing an Interrupt bit
(1)
1 = CPU gets High Priority access to SRAM
0 = CPU uses Least Recently Serviced Arbitration (same as other initiators)
bit 23-18 Unimplemented: Read as ‘0’
bit 17 ICACLK: Input Capture Alternate Clock Selection bit
(1)
1 = Input Capture modules use an alternative Timer pair as their timebase clock
0 = All Input Capture modules use Timer2/3 as their timebase clock
bit 16 OCACLK: Output Compare Alternate Clock Selection bit
(1)
1 = Output Compare modules use an alternative Timer pair as their timebase clock
0 = All Output Compare modules use Timer2/3 as their timebase clock
bit 15-14 Unimplemented: Read as ‘0’
bit 13 IOLOCK: Peripheral Pin Select Lock bit
(1)
1 = Peripheral Pin Select is locked. Writes to PPS registers are not allowed
0 = Peripheral Pin Select is not locked. Writes to PPS registers are allowed
bit 12 PMDLOCK: Peripheral Module Disable bit
(1)
1 = Peripheral module is locked. Writes to PMD registers are not allowed
0 = Peripheral module is not locked. Writes to PMD registers are allowed
bit 11 PGLOCK: Permission Group Lock bit
(1)
1 = Permission Group registers are locked. Writes to PG registers are not allowed
0 = Permission Group registers are not locked. Writes to PG registers are allowed
bit 10-9 Unimplemented: Read as ‘0’
bit 8 USBSSEN: USB Suspend Sleep Enable bit
(1)
Enables features for USB PHY clock shutdown in Sleep mode.
1 = USB PHY clock is shut down when Sleep mode is active
0 = USB PHY clock continues to run when Sleep is active
Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 42. “Oscillators with
Enhanced PLL” in the “PIC32 Family Reference Manual” for details.