Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 593
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 34-5: DEVCFG2/ADEVCFG2: DEVICE CONFIGURATION WORD 2
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
r-1 R/P r-1 r-1 r-1 r-1 r-1 r-1
— UPLLFSEL — — — — — —
23:16
r-1 r-1 r-1 r-1 r-1 R/P R/P R/P
— — — — — FPLLODIV<2:0>
15:8
r-1 R/P R/P R/P R/P R/P R/P R/P
FPLLMULT<6:0>
7:0
R/P R/P R/P R/P r-1 R/P R/P R/P
FPLLICLK FPLLRNG<2:0> — FPLLIDIV<2:0>
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: Write as ‘1’
bit 30 UPLLFSEL: USB PLL Input Frequency Select bit
1 = UPLL input clock is 24 MHz
0 = UPLL input clock is 12 MHz
bit 29-19 Reserved: Write as ‘1’
bit 18-16 FPLLODIV<2:0>: Default System PLL Output Divisor bits
111 = PLL output divided by 32
110 = PLL output divided by 32
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 2
bit 15 Reserved: Write as ‘1’
bit 14-8 FPLLMULT<6:0>: System PLL Feedback Divider bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
bit 7 FPLLICLK: System PLL Input Clock Select bit
1 = FRC is selected as input to the System PLL
0 =P
OSC is selected as input to the System PLL
bit 6-4 FPLLRNG<2:0>: System PLL Divided Input Clock Frequency Range bits
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass