Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 59
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 3-10: FCSR: FLOATING POINT CONTROL AND STATUS REGISTER; CP1 REGISTER 31
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
FCC<7:1> FS
23:16
R/W-x R/W-x R/W-x R-0 R-1 R-1 R/W-x R/W-x
FCC<0> FO FN MAC2008 ABS2008 NAN2008 CAUSE<5:4>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CAUSE<3:0>
ENABLES<4:1>
VZOU
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ENABLES<0> FLAGS<4:0>
RM<1:0>
IVZOUI
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 FCC<7:1>: Floating Point Condition Code bits
These bits record the results of floating point compares and are tested for floating point conditional
branches and conditional moves.
bit 24 FS: Flush to Zero control bit
1 = Denormal input operands are flushed to zero. Tiny results are flushed to either zero or the applied
format's smallest normalized number (MinNorm) depending on the rounding mode settings.
0 = Denormal input operands result in an Unimplemented Operation exception.
bit 23 FCC<0>: Floating Point Condition Code bits
These bits record the results of floating point compares and are tested for floating point conditional branches
and conditional moves.
bit 22 FO: Flush Override Control bit
1 = The intermediate result is kept in an internal format, which can be perceived as having the usual
mantissa precision but with unlimited exponent precision and without forcing to a specific value or
taking an exception.
0 = Handling of Tiny Result values depends on setting of the FS bit.
bit 21 FN: Flush to Nearest Control bit
1 = Final result is rounded to either zero or 2E_min (MinNorm), whichever is closest when in Round to
Nearest (RN) rounding mode. For other rounding modes, a final result is given as if FS was set to 1.
0 = Handling of Tiny Result values depends on setting of the FS bit.
bit 20 MAC2008: Fused Multiply Add mode control bit
0 = Unfused multiply-add. Intermediary multiplication results are rounded to the destination format.
bit 19 ABS2008: Absolute value format control bit
1 = ABS.fmt and NEG.fmt instructions compliant with IEEE Standard 754-2008. The ABS and NEG functions
accept QNAN inputs without trapping.
bit 18 NAN2008: NaN Encoding control bit
1 = Quiet and signaling NaN encodings recommended by the IEEE Standard 754-2008. A quiet NaN is
encoded with the first bit of the fraction being 1 and a signaling NaN is encoded with the first bit of the
fraction being 0.
bit 17-12 CAUSE<5:0>: FPU Exception Cause bits
These bits indicated the exception conditions that arise during execution of an FPU arithmetic instruction.
bit 17 E: Unimplemented Operation bit