Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 589

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

bit 10 FSLEEP: Flash Sleep Mode bit

1 = Flash is powered down when the device is in Sleep mode

0 = Flash remains powered when the device is in Sleep mode

bit 9-8 FECCCON<1:0>: Dynamic Flash ECC Configuration bits

Upon a device Reset, the value of these bits is copied to the ECCCON<1:0> bits (CFGCON<5:4>).

11 = ECC and dynamic ECC are disabled (ECCCON<1:0> bits are writable)

10 = ECC and dynamic ECC are disabled (ECCCON<1:0> bits are locked)

01 = Dynamic Flash ECC is enabled (ECCCON<1:0> bits are locked)

00 = Flash ECC is enabled (ECCCON<1:0> bits are locked; disables word Flash writes)

bit 7 Reserved: Write as ‘1’

bit 6 BOOTISA: Boot ISA Selection bit

1 = Boot code and Exception code is MIPS32

®

(ISAONEXC bit is set to ‘0’ and the ISA<1:0> bits are set to ‘10’ in the CP0 Config3 register)

0 = Boot code and Exception code is microMIPS™

(ISAONEXC bit is set to ‘1’ and the ISA<1:0> bits are set to ‘11’ in the CP0 Config3 register)

bit 5 TRCEN: Trace Enable bit

1 = Trace features in the CPU are enabled

0 = Trace features in the CPU are disabled

bit 4-3 ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits

11 = PGEC1/PGED1 pair is used

10 = PGEC2/PGED2 pair is used

01 = Reserved

00 = Reserved

bit 2 JTAGEN: JTAG Enable bit

(1)

1 = JTAG is enabled

0 = JTAG is disabled

bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)

1x = Debugger is disabled

0x = Debugger is enabled

Note 1: This bit sets the value of the JTAGEN bit in the CFGCON register.