Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 588 Preliminary  2015 Microchip Technology Inc.
REGISTER 34-3: DEVCFG0/ADEVCFG0: DEVICE CONFIGURATION WORD 0
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
r-x R/P r-1 r-1 r-1 r-1 r-1 r-1
— EJTAGBEN — — — — — —
23:16
r-1 r-1 R/P R/P R/P R/P R/P R/P
— — POSCBOOST
POSCGAIN<1:0>
SOSCBOOST
SOSCGAIN<1:0>
15:8
R/P R/P R/P R/P r-y R/P R/P R/P
SMCLR DBGPER<2:0> — FSLEEP FECCCON<1:0>
7:0
r-1 R/P R/P R/P R/P R/P R/P R/P
— BOOTISA TRCEN ICESEL<1:0> JTAGEN
(1)
DEBUG<1:0>
Legend: r = Reserved bit y = Value set from Configuration bits on POR
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: The reset value of this bit is the same as DEVSIGN0<31>.
bit 30 EJTAGBEN: EJTAG Boot Enable bit
1 = Normal EJTAG functionality
0 = Reduced EJTAG functionality
bit 29-22 Reserved: Write as ‘1’
bit 21 POSCBOOST: Primary Oscillator Boost Kick Start Enable bit
1 = Boost the kick start of the oscillator
0 = Normal start of the oscillator
bit 20-19 POSCGAIN<1:0>: Primary Oscillator Gain Control bits
11 = 2x gain setting
10 = 1.5x gain setting
01 = 0.5x gain setting
00 = 1x gain setting
bit 18 SOSCBOOST: Secondary Oscillator Boost Kick Start Enable bit
1 = Boost the kick start of the oscillator
0 = Normal start of the oscillator
bit 17-16 SOSCGAIN<1:0>: Secondary Oscillator Gain Control bits
11 = 2x gain setting
10 = 1.5x gain setting
01 = 0.5x gain setting
00 = 1x gain setting
bit 15 SMCLR: Soft Master Clear Enable bit
1 = MCLR
pin generates a normal system Reset
0 = MCLR
pin generates a POR Reset
bit 14-12 DBGPER<2:0>: Debug Mode CPU Access Permission bits
1xx = Allow CPU access to Permission Group 2 permission regions
x1x = Allow CPU access to Permission Group 1 permission regions
xx1 = Allow CPU access to Permission Group 0 permission regions
0xx = Deny CPU access to Permission Group 2 permission regions
x0x = Deny CPU access to Permission Group 1 permission regions
xx0 = Deny CPU access to Permission Group 0 permission regions
When the CPU is in Debug mode and the CPU1PG<1:0> bits (CFGPG<1:0>) are set to a denied permission
group as defined by DBGPER<2:0>, the transaction request is assigned Group 3 permissions.
bit 11 Reserved: This bit is controlled by debugger/emulator development tools and should not be modified by
the user.
Note 1: This bit sets the value of the JTAGEN bit in the CFGCON register.